Sung Woo Hwang

Dense dislocation arrays embedded in grain boundaries for high-performance bulk thermoelectrics

Squeezing out efficient thermoelectrics Thermoelectric materials hold the promise of converting waste heat into electricity. The challenge is to develop high-efficiency materials that are not too expensive. Kim et al. suggest a pathway for developing inexpensive thermoelectrics. They show a dramatic improvement of efficiency in bismuth telluride samples by quickly squeezing out excess liquid during compaction. This method introduces grain boundary dislocations in a way that avoids degrading electrical conductivity, which makes a better thermoelectric material. With the potential for scale-up and application to cheaper materials, this discovery presents an attractive path forward for thermoelectrics. Science, this issue p. 109 Pressure-assisted liquid-phase compaction allows synthesis of high–conversion efficiency thermoelectric materials. The widespread use of thermoelectric technology is constrained by a relatively low conversion efficiency of the bulk alloys, which is evaluated in terms of a dimensionless figure of merit (zT). The zT of bulk alloys can be improved by reducing lattice thermal conductivity through grain boundary and point-defect scattering, which target low- and high-frequency phonons. Dense dislocation arrays formed at low-energy grain boundaries by liquid-phase compaction in Bi0.5Sb1.5Te3 (bismuth antimony telluride) effectively scatter midfrequency phonons, leading to a substantially lower lattice thermal conductivity. Full-spectrum phonon scattering with minimal charge-carrier scattering dramatically improved the zT to 1.86 ± 0.15 at 320 kelvin (K). Further, a thermoelectric cooler confirmed the performance with a maximum temperature difference of 81 K, which is much higher than current commercial Peltier cooling devices.

Non-enzymatic electrochemical CuO nanoflowers sensor for hydrogen peroxide detection

The electrocatalytic activity of a CuO flower-like nanostructured electrode was investigated in terms of its application to enzyme-less amperometric H(2)O(2) sensors. The CuO nanoflowers film was directly formed by chemical oxidation of copper foil under hydrothermal condition and then used as active electrode material of non-enzymatic electrochemical sensors for H(2)O(2) detection under alkaline conditions. The sensitivity of the sensor with CuO nanoflowers electrode was 88.4 microA/mM cm(2) with a linear response in the range from 4.25 x 10(-5) to 4 x 10(-2)M and a detection limit of 0.167 microM (S/N=3). Excellent electrocatalytic activity, large surface-to-volume ratio and efficient electron transport property of CuO nanoflowers electrode have enabled stable and highly sensitive performance for the non-enzymatic H(2)O(2) sensor.

Catalyst-free growth of single-crystal silicon and germanium nanowires.

We report metal-free synthesis of high-density single-crystal elementary semiconductor nanowires with tunable electrical conductivities and systematic diameter control with narrow size distributions. Single-crystal silicon and germanium nanowires were synthesized by nucleation on nanocrystalline seeds and subsequent one-dimensional anisotropic growth without using external catalyst. Systematic control of the diameters with tight distribution and tunable doping concentration were realized by adjusting the growth conditions, such as growth temperature and ratio of precursor partial pressures. We also demonstrated both n-type and ambipolar field effect transistors using our undoped and phosphorus-doped metal-free silicon nanowires, respectively. This growth approach offers a method to eliminate potential metal catalyst contamination and thus could serve as an important point for further developing nanowire nanoelectronic devices for applications.

Macromodeling of single-electron transistors for efficient circuit simulation

In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors can be used for efficient circuit simulation. The developed macromodel produces simulation results with reasonable accuracy and with orders of magnitude less CPU time than usual Monte Carlo simulations.

Graphene for true Ohmic contact at metal-semiconductor junctions.

The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8) ~ 10(-9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).

Relativistic entanglement and Bell's inequality

In this paper, the Lorentz transformation of entangled Bell states seen by a moving observer is studied. The calculated Bell observable for four joint measurements turns out to give a universal value, + + - =(2/{radical}(2-{beta}{sup 2}))(1+{radical}(1-{beta}{sup 2})), where a,b are the relativistic spin observables derived from the Pauli-Lubanski pseudovector and {beta}=(v/c). We found that the degree of violation of the Bells inequality is decreasing with increasing velocity of the observer and Bells inequality is satisfied in the ultrarelativistic limit where the boost speed reaches the speed of light.

Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Si single-electron transistors with sidewall depletion gates on a silicon-on-insulator nanowire are proposed and fabricated, using the combination of conventional lithography and process technology. The size dependence of device characteristics shows good controllability and reproducibility, and a dynamic multi-functional SET logic is successfully demonstrated at 10 K, for the first time.

Observation of Single Electron Tunneling and Ballistic Transport in Twin Silicon Nanowire MOSFETs (TSNWFETs) Fabricated by Top-Down CMOS Process

the authors report transport experiments on gate-all-around (GAA) TSNWFETs fabricated by top-down CMOS processes. The nanowire with 45 nm gate length exhibits single electron tunneling, and the total capacitance extracted from the measured data is in good agreement with the self-capacitance of an ideal cylinder. The nanowire with 125 nm gate length shows conductance quantization suggesting ballistic transport. The temperature dependence of the conductance steps is consistent with the crossover from classical to ballistic

Large Work Function Modulation of Monolayer MoS2 by Ambient Gases

Although two-dimensional monolayer transition-metal dichalcogenides reveal numerous unique features that are inaccessible in bulk materials, their intrinsic properties are often obscured by environmental effects. Among them, work function, which is the energy required to extract an electron from a material to vacuum, is one critical parameter in electronic/optoelectronic devices. Here, we report a large work function modulation in MoS2 via ambient gases. The work function was measured by an in situ Kelvin probe technique and further confirmed by ultraviolet photoemission spectroscopy and theoretical calculations. A measured work function of 4.04 eV in vacuum was converted to 4.47 eV with O2 exposure, which is comparable with a large variation in graphene. The homojunction diode by partially passivating a transistor reveals an ideal junction with an ideality factor of almost one and perfect electrical reversibility. The estimated depletion width obtained from photocurrent mapping was ∼200 nm, which is much narrower than bulk semiconductors.

Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges

On the basis of 2-D potential analysis performed while taking into account the effective conducting path effect, a new analytical model for threshold voltage in cylindrical surrounding-gate MOSFETs (SGMOSFETs) that contain localized charges is presented. From the 2-D Poissons equation based on a parabolic potential approximation, a simple and accurate analytical expression for the threshold voltage is derived. The proposed model is validated using a 3-D device simulator, and good agreement is obtained for various device dimensions and charge distributions. This model can be used to investigate hot-carrier-induced degradation of SGMOSFETs.