Tan Fu Lei

An analytical model for the above-threshold characteristics of polysilicon thin-film transistors

An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFTs) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E/sub c/-0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias. >

The effects of fluorine passivation on polysilicon thin-film transistors

The fluorine implantation on polysilicon was found to improve the characteristics of polysilicon thin-film transistors (TFTs). The fluorine passivates the trap states within the polysilicon channel, as compared with the H/sub 2/-plasma passivation. The fluorine implantation passivates more uniformly both the band tail-states and midgap deep-state, while the H/sub 2/-plasma treatment is more effective to passivate deep states than tail states. A fluorine-implanted device can be further improved its performance if an H/sub 2/-plasma treatment is applied. In contrast to the H/sub 2/-plasma passivation, the fluorine passivation improves the device hot-carrier immunity. Combining the fluorine passivation and H/sub 2/-plasma passivation, a high performance TFT with a high hot-carrier immunity can be obtained. >

High-k cobalt-titanium oxide dielectrics formed by oxidation of sputtered Co/Ti or Ti/Co films

High-k cobalt–titanium oxide (CoTiO3) film was formed by directly oxidizing sputtered Co/Ti or Ti/Co films. Al/CoTiO3/Si3N4/Si capacitor structures were fabricated and measured. Excellent electrical properties with an effective dielectric constant (i.e., k value) as high as 40 have been achieved for a CoTiO3 gate dielectric with a buffer layer. The metal–oxide thus appears to be a very promising high-k gate dielectric for future ultralarge scale integrated devices.

Reliability Mechanisms of LTPS-TFT With

In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the gate dielectric is observed for the PBS and PBTI of the LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the LTPS-TFT.

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A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm/sup 2//V-s, ON/OFF current ratio of 1.1 10/sup 7/, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFTs.

Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress

The effects of H/sub 2/-plasma followed by O/sub 2/-plasma treatment on n-channel polysilicon thin-film transistors (TFTs) were investigated. It was found that the H/sub 2/-O/sub 2/-plasma treatment is more effective in passivating the trap states of polysilicon films than the H/sub 2/-plasma or O/sub 2/-plasma treatment only. Hence, it is more effective in improving the device performance with regard to subthreshold swing, carrier mobility, and the current ON/OFF ratio. It is also found that thermal annealing of plasma-treated devices increases the deep states but has no effect on the tail states of the devices. >

Fabrication of thin film transistors by chemical mechanical polished polycrystalline silicon films

For the first time, the characteristics and temperature dependence of electrical properties for ultrathin HfO 2 gate dielectrics treated in NH 3 plasma after deposition were investigated. After this treatment, significantnitrogen incorporation at the HfO 2 /silicon interface (interfacial layer) was examined by Auger electron spectroscopy. Moreover, the formation of Hf-N bonding and the suppression of Hf-Si bonding were observed from electron spectroscopy for chemical analysis spectra. The activation energy of charge trapping reflected in the current-voltage characteristics was effectively reduced, which led to improved hysteresis and its weaker temperature dependence in HfO 2 gate dielectrics treated in NH 3 plasma.

The effects of H/sub 2/-O/sub 2/-plasma treatment on the characteristics of polysilicon thin-film transistors

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO/sub 2/ interface. An atomically flat Si/SiO/sub 2/ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p/sup +/ poly-Si gate MOS devices even with the annealing temperature as high as 1000/spl deg/C.<<ETX>>

Characterization of temperature dependence for HfO2 gate dielectrics treated in NH3 plasma

N/sub 2/O was used to grow silicon polyoxide. It was found that the N/sub 2/O-grown polyoxide had a lower leakage current but a higher breakdown field when the top-electrode was positively biased. This is opposite to that of conventional O/sub 2/-grown polyoxide. Moreover, it had less electron trapping when stressed and a larger charge-to-breakdown. >

Suppression of the boron penetration induced Si/SiO/sub 2/ interface degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

dMerck-Kanto, Advanced Chemicals Limited, Taoyuan, Taiwan This work proposes an advanced wet chemical one-step cleaning process which omits the hydrochloric acid/hydrogen peroxide/ water mixture ~HPM! step in RCA. A novel one-step cleaning solution had been developed for pregate oxide cleaning to replace the conventional RCA two-step cleaning recipe, which used ammonia/hydrogen peroxide ~or SC-1! and HPM ~or SC-2! step. Tetramethylammonium hydroxide ~TMAH! and ethylenediaminetetraacetic acid ~EDTA! were added into the RCA SC-1 cleaning solution to enhance cleaning efficiency. From the experimental results, the particles and metallic contamination on the bare Si wafer surface could be removed significantly by applying this one-step cleaning solution. The effectiveness of various cleaning recipes and their interaction mechanism with silicon surfaces were studied. The surface adsorption and double layer models could explain the surface behavior of TMAH solutions. Based on the model, the particle, surface roughness and metallic contaminants can be realized. It was observed that the electrical properties of metal oxide semiconductor capacitors after cleaning with this novel solution were better than those after the conventional RCA cleaning. Besides, the cleaning method combining NH4OH, tetramethylammonium hydroxide, ethylenediaminetetraacetic acid, and H2O2, at 80°C for 3 min showed high performance on particle removal, metal cleaning, surface smoothness, and electrical properties. Hence, this one-step cleaning process is very promising for future large sized silicon wafer cleaning due to the advantages of time-saving, low cost, and high performance.