Yunpeng Lu

An antimatter spectrometer in space

Abstract We discuss a simple magnetic spectrometer to be installed on a satellite or space station. The purpose of this spectrometer is to search for primordial antimatter to the level of antimatter/matter ≈10 −9 , improving the existing limits obtained with balloon flights by a factor of 10 4 to 10 5 . The design of the spectrometer is based on an iron-free, Ndue5f8Feue5f8B permanent magnet, scintillation counters, drift tubes, and silicon or time projection chambers. Different design options are discussed. Typically, the spectrometer has a weight of about 2 tons and an acceptance of about 1.0 m 2 sr. The availability of the new Ndue5f8Feue5f8B material makes it possible for the first time to put a magnet into space economically and reliably.

FPGA - Based Compute Nodes for the PANDA Experiment at FAIR

PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb Is. FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. High bandwidth connectivity is provided by four Gbit Ethernet links and 8 additional optical links connected to RocketIO ports. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane.

FPGA based high speed data transmission with optical fiber in trigger system of BESIII

The article described a new design of high-speed data transmission, used in BESIII trigger system, with optical fibre that was based on the on-chip serial/deserial transceiver in FPGA. A special custom protocol is defined to transfer the consecutive and real-time data, recover and process the data belongs to the same event at the same time. The design was tested for a long period run. A high level of confidence bit error rate was obtained, and all channels from different transmitters were re-aligned by using unfixed delay alignment method. The design was implemented in the trigger system and would meet the requirements of BESIII.

Trigger System of BESIII

The trigger system of Beijing Spectrometer III, part of the upgrade of Beijing Electron Positron Collider, has been designed and implemented, and is ready for installation. This paper describes briefly the system components, its characteristics, and some technical issues. The system consists mainly of four parts: MDC (drift chamber) tracking subsystem, EMC (electromagnetic calorimeter) subsystem, TOF (time of flight) subsystem and global trigger. Some highlights in designing of this system includes: trigger scheme optimization with software simulation; optical transmission between trigger and FEEs to realize isolation with FEEs to avoid ground loop current interference; designed with most latest FPGA (Xilinx Spartan 3, VirtexII Pro...) for simplicity, high reliability and easy maintenance and hence smaller system; FPGA in-system programming or firmware online downloadable via onboard, panel connector and/or VME bus for modification flexibility during commissioning. Different from the usual fix delay data transmission from FEE to trigger, the RocketIO has been used as SEDES.

Evaluation of a pulse counting type SOI pixel using synchrotron radiation X-ray

Silicon-On-Insulator (SOI) technology was used to develop a fine pixelated detector with high performance. The first beam test for a prototype pulse-counting-type SOI chip, CPIXTEG3b, was performed at beamline BL-14A of the Photon Factory, KEK. CPIXTEG3b was designed using double SOI technology for decreasing crosstalk and increasing radiation hardness. It has a 64 × 64 pixel array wherein each pixel size is 50 μm × 50 μm. The sensitivity to incident X-rays was measured for each pixel with an X-ray beam 10 μm in diameter. We used the X-ray energy of 16 keV. Because of its small size, the pixel response was sensitive to the charge-sharing effect. We also considered the point spread function of the sensor. The discriminator of each pixel circuit was calibrated using a pulse generator, and performance was checked using flat-field X-rays.

HEPS-BPIX, a hybrid pixel detector system for the High Energy Photon Source in China

A hybrid pixel detector with single photon counting mode has been designed for the High Energy Photon Source in China. It features a pixel size of 150 μm × 150 μm and a frame rate up to 1.2 kHz with 20-bit dynamic range. Six modules were assembled as the first prototype system, covering an area of 9 cm × 10 cm with 360k pixels. Images have been taken using X-ray and synchrotron radiation light, and the preliminary detector performance is presented.

A High Frame Rate Test System for the HEPS-BPIX Based on NI-sbRIO Board

HEPS-BPIX is a silicon pixel detector designed for the future large scientific facility, high-energy photon sources (HEPS) in Beijing, China. It is a high frame rate hybrid pixel detector which works in the single-photon-counting mode. High frame rate leads to much higher readout data bandwidth than former systems, which is also the difficulty of the design. Aiming to test and calibrate the pixel detector, a test system based on the National Instruments single-board RIO 9626 and LabVIEW program environment has been designed. A series of tests has been carried out with X-ray machine as well as on the Beijing Synchrotron Radiation Facility 1W2B beamline. The test results show that the threshold uniformity is better than 60 electrons and the equivalent noise charge is less than 120 electrons. Besides, the required highest frame rate of 1.2 kHz has been realized. This paper will elaborate the test system design and present the latest testing results of the HEPS-BPIX system.

Development of a new high-speed readout system for SOI pixel detectors

Abstract We are developing a new high-speed readout system for silicon on insulator (SOI) pixel detectors. The SOI detector is a monolithic radiation imaging detector based on a 0.2 μ m FD-SOI CMOS process. Previously, we used a Xilinx Virtex-4/5 FPGA readout board for the SOI detector and developed many facilities for this board. However, the Virtex-4/5 FPGA is now obsolete and does not have sufficiently high performance for recent experiments that require more than 1-kHz high-speed imaging with a large number of pixels. Thus, we started to develop a new high-speed readout system using the KC705, which is the evaluation board for the Xilinx Kintex-7 FPGA. We developed a new data acquisition structure that has backward compatibility with the previous environment on this board and implements several functions for practical purposes such as micro Computed Tomography. The transfer speed achieved by the new system is 95.3 fps for a 426k pixel detector in continuous data-taking mode, and 762.5 fps in maximum-speed mode. The details of the new readout system are presented.

Synchrotron beam test of a photon counting pixel prototype based on Double-SOI technology

The overall noise performances and first synchrotron beam measurement results of CPIXETEG3b, the first counting type Silicon-On-Insulator (SOI) pixel sensor prototype without crosstalk issue, are reported. The prototype includes a 64 × 64 pixel matrix with 50 μm pitch size. Each pixel consists of an N-in-P charge collection diode, a charge sensitive preamplifier, a shaper, a discriminator with thresholds adjustable by an in-pixel 4-bit DAC, and a 6-bit counter. The study was performed using the beam line 14A at KEK Photon Factory (KEK-PF) . The homogeneous response of the prototype, including charging-sharing effects between pixels were studied. 16 keV and 8 keV monochromatic small size (~ 10 μm diameter) X-ray beams were used for the charge sharing study, and a flat-field was added for homogenous response investigation. The overall detector homogeneity and the influence of basic detector parameters on charge sharing between pixels has been investigated.

Development of Fast Readout System for Counting-Type SOI Detector ‘CNPIX’

We are developing a data readout system for a new photon-counting type SOI detector ‘CNPIX’. CNPIX detector will contain ~100 k hexagonal pixels and frame rates more than 1 kHz is demanded to observe dynamic structure of the samples. We adopt KC705 evaluation board equipped with Kintex-7 FPGA, DDR3 memory, and Gigabit Ethernet interface as the base of our new system to meet this demand. The CNPIX detector signals are connected through FPGA mezzanine card interface.