Yunyou Lu

600-V Normally Off

In this letter, 600-V normally-OFF SiNx/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is reported. Normally-OFF operation and low OFF-state gate leakage are obtained by using fluorine plasma ion implantation in conjunction with the adoption of a 17-nm SiNx thin film grown by plasma-enhanced chemical vapor deposition as the gate insulator. The normally-OFF MIS-HEMT exhibits a threshold voltage of +3.6 V, a drive current of 430 mA/mm at a gate bias of 14 V, a specific ON-resistance of 2.1 mΩ·cm2 and an OFF-state breakdown voltage of 604 V at a drain leakage current of 1 μA/mm with VGS=0 V, and the substrate grounded. Effective current collapse suppression is obtained by AlN/SiNx passivation as proved by high-speed pulsed I-V and low-speed high-voltage switching measurement results.

{\rm SiN}_{x}

We report an in situ low-damage pre-gate treatment technology in an atomic layer deposition (ALD) system prior to the ALD- Al₂O₃ deposition, to realize high-quality Al₂O₃/III-nitride (III-N) interface. The technology effectively removes the poor quality native oxide on the III-N surface while forming an ultrathin monocrystal-like nitridation interlayer (NIL) between Al₂O₃ and III-N surface. With the pre-gate treatment technology, high-performance Al₂O₃(NIL)/GaN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors are demonstrated, exhibiting well-behaved electrical characteristics including suppressed gate leakage current, a small subthreshold slope of ~64 mV/dec, and a small hysteresis of ~0.09 V.

/AlGaN/GaN MIS-HEMT With Large Gate Swing and Low Current Collapse

With an in situ low-damage NH₃-Ar-N₂ plasma pre-gate treatment, a high-quality Al₂O₃/GaN-cap interface has been obtained in the Al₂O₃/GaN/AlGaN/GaN MIS-structures. Frequency- and temperature-dependent C-V characterization techniques were developed to map the interface trap density (D_it) at the dielectric/III-nitride interface, whereby a low D_it of ~10¹²-10¹³ cm^-2eV^-1 in the Al₂O₃/GaN/AlGaN/GaN MIS-structures was extracted. The mechanism for the high-quality interface was validated to be effective removal of native oxide and the subsequent formation of a monocrystal-like nitridation inter-layer on the GaN surface. Both D_it mapping and the pre-gate treatment techniques are of significance for the improvement of III-nitride MIS-HEMTs.

High-Quality Interface in

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth.

{\rm Al}_{2}{\rm O}_{3}/{\rm GaN}/{\rm GaN}/{\rm AlGaN}/{\rm GaN}

We demonstrate high-voltage depletion-mode and enhancement-mode (E-mode) AlGaN/GaN high-electron-mobility transistors (HEMTs) on a GaN-on-silicon-on-insulator (SOI) platform. The GaN-on-SOI wafer features GaN epilayers grown by metal-organic chemical vapor deposition on a p-type (111) Si SOI substrate with a p-type (100) Si handle wafer. Micro-Raman spectroscopy significantly reveals reduced stress in the GaN epilayers, which is a result expected from the compliant SOI substrate. E-mode HEMTs fabricated by fluorine plasma implantation technique deliver high on/off current ratio (108-109), large breakdown voltage (1471 V with floating substrate), and low on-resistance (3.92 mΩ·cm2).

MIS Structures With In Situ Pre-Gate Plasma Nitridation

The mechanisms of divergent VTH-thermal-stabilities of III-nitride (III-N) MIS-HEMT and MOS-Channel-HEMT are revealed in this work. The more significant VTH-thermal-instability of MIS-HEMT is attributed to the polarized III-N barrier layer that spatially separates the critical gate-dielectric/III-N interface from the channel and allows “deeper” interface trap levels emerging above the Fermi level at pinch-off. We also reveal the influences of the barrier layers thickness and the fixed charges (e.g. F-) in the barrier layer on VTH-thermal-stability and attempt to provide guidelines for the optimization of insulated-gate III-N power switching devices. A tailor-made normally-off MIS-HEMT with optimal tradeoff between performance and stability is thereby demonstrated, by conjunctively utilizing partially recessed gate and fluorine plasma implantation techniques.

Mapping of interface traps in high-performance Al 2 O 3 /AlGaN/GaN MIS-heterostructures using frequency- and temperature-dependent C-V techniques

A low on-resistance normally-off GaN double-channel metal-oxide-semiconductor high-electronmobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with Vth of +0.5 V at IDS = 10 μA/mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/(V·s). The on-resistance is as small as 6.9 Q·mm for a DC-MOS-HEMT with LG/LGS/LGD = 1.5/2/15 μm, and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. Index Terms-Double-channel MOS-HEMT (DC-MOSHEMT), field-effect mobility, gate recess, normally-off.

AC-Capacitance Techniques for Interface Trap Analysis in GaN-Based Buried-Channel MIS-HEMTs

A high-temperature (180 °C) gate recess technique featuring low damage and in-situ self-clean capability, in combination with O₃-assisted atomic-layer-deposition (ALD) of Al₂O₃ gate dielectric, is developed for fabrication of high performance normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs), which exhibit a threshold voltage of +1.6 V, a pulsed drive current of 1.1 A/mm, and low dynamic ON-resistance under hard-switching operation. Chlorine-based dry-etching residues (e.g. AlCl₃ and GaCl₃) are significantly reduced by increasing the wafer temperature during the gate recess to their characteristic desorption temperature, while defective bonds like Al-O-H and positive fixed charges in ALD-Al₂O₃ are significantly suppressed by substitution of H₂O with O₃ precursor.

1.4-kV AlGaN/GaN HEMTs on a GaN-on-SOI Platform

An enhancement-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) was fabricated on a double-channel heterostructure, which features a 1.5-nm AlN layer (AlN-ISL) inserted 6 nm below the conventional barrier/GaN hetero-interface, forming a lower channel at the interface between AlN-ISL and the underlying GaN. With the gate recess terminated at the upper GaN channel layer, a positive threshold voltage is obtained, while the lower channel retains its high 2DEG mobility as the heterojunction is preserved. The fabricated device delivers a small on-resistance, large current, high breakdown voltage, and sharp subthreshold swing. The large tolerance for gate recess depth is also confirmed by both simulation and experiment.

Thermally induced threshold voltage instability of III-Nitride MIS-HEMTs and MOSC-HEMTs: Underlying mechanisms and optimization schemes

In this work, we attempt to reveal the underlying mechanisms of divergent VTH-thermal-stabilities in III-nitride metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) and MOS-Channel-HEMT (MOSC-HEMT). In marked contrast to MOSC-HEMT featuring temperature-independent VTH, MIS-HEMT with the same high-quality gate-dielectric/III-nitride interface and similar interface trap distribution exhibits manifest thermally induced VTH shift. The temperature-dependent VTH of MIS-HEMT is attributed to the polarized III-nitride barrier layer, which spatially separates the critical gate-dielectric/III-nitride interface from the channel and allows “deeper” interface trap levels emerging above the Fermi level at pinch-off. This model is further experimentally validated by distinct VG-driven Fermi level movements at the critical interfaces in MIS-HEMT and MOSC-HEMT. The mechanisms of polarized III-nitride barrier layer in influencing VTH-thermal-stability provide guidelines for the optimization of insula...