Yusuke Iguchi

An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation at 0.42 V in a 90-nm 64-Mb SRAM is possible under dynamic voltage scaling (DVS) environment.

Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential —

This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can operate fastest, because its small differential voltage of 50 mV achieves the high-speed operation. In terms of the power efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM.

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing

We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have special correlation and similar data are read out in consecutive cycles. As well as the power reduction, the precharge-less structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% reduction) on the bitlines, and saves 74% of a readout power when considered as an H.264 reconstructed-image memory. The area overhead is 14.4% in a 90-nm process technology.

Control of signalling properties of human somatostatin receptor subtype 5 by additional signal sequences on its amino-terminus in yeast

The yeast Saccharomyces cerevisiae is known as an available host for human G-protein-coupled receptor (GPCR) ligand screening. Although several types of yeast signal sequences (SS) attached with the GPCRs could improve their productivities and facilitate transportation of the GPCRs to the yeast plasma membrane, the effects of additional SS on ligand-specific signalling functions of GPCRs are not reported. Here, we demonstrated the controlling signalling properties by addition of SS using engineered yeast as a host. Prepro and pre regions of alpha-factor and amino-terminal sequence of Ste2 (Ste2N) were used as SS, and somatostatin (SST) receptor subtype-5 (SSTR5) was used as a model GPCR. We also constructed a yeast-based fluorescent assay system for monitoring the activation levels of SSTR5 signalling by a green fluorescent protein (GFP) reporter gene. The production levels and localisation patterns of the SS-attached SSTR5 were more significantly improved than those of wild-type SSTR5. In addition, we successfully controlled the pharmacological efficacy and potency by introducing SS. Among four types of SSTR5 receptors, Ste2N-SSTR5 responded at the lowest ligand concentration. This finding will be informative for constructing optimal yeast-based ligand screening systems to discriminate the cells on the basis of signalling levels.

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme

We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V.

Transplantation of the GAL regulon into G-protein signaling circuitry in yeast

Here we present a successful transplantation of the GAL genetic regulatory circuitry into the G-protein signaling pathway in yeast. The GAL regulon represents a strictly regulated transcriptional mechanism that we have transplanted into yeast to create a highly robust induction system to assist the detection of on-off switching in G-protein signaling. In our system, we engineered yeast to drive the positive GAL regulatory gene in response to agonist-promoted G-protein signaling and to induce transcription of a green fluorescent protein (GFP) reporter gene under the control of the GAL structural gene promoter. Consequently, in response to agonist stimulation of G-protein-coupled receptors (GPCRs), the engineered yeast achieved more than a 150-fold increase in reporter intensity in up to 98% of cells, as determined by flow cytometric sorting. Surprisingly, agonist-stimulated induction of the GFP reporter gene was higher than that by galactose. Our approach to boost reporter gene induction could be applicable in establishing more efficient yeast-based flow cytometric screening systems for agonistic ligands for heterogeneous GPCRs.

Area Optimization in 6T and 8T SRAM Cells Considering V th Variation in Future Processes

This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.

Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential

As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The Vth variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T SRAM has the lowest transistor count, and is the most area efficient. However, the readout power becomes large and the access time increases because of peripheral circuits. The 10T single-end SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port, can reduce the readout power by 74%. The operating frequency is improved by 195%, over the 8T SRAM. However, the 10T differential SRAM can operate fastest (256% faster than the 8T SRAM) because its small differential voltage of 50mV achieves high-speed operation. In terms of the power efficiency, however, the readout current is affected by the Vth variation and the timing of sense cannot be optimized singularly among all memory cells in a 45-nm technology. The readout power remains 34% lower than that of the 8T SRAM (33% higher than the 10T single-end SRAM); even its operating voltage is the lowest of the three. The 10T single-end SRAM always consumes less readout power than the 8T or 10T differential SRAM.

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the area.