Yusuke Matsunaga

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Develops multi-level logic minimization programs using binary decision diagram (BDD). The authors present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.<<ETX>>

Multi-level logic optimization using binary decision diagrams

A multilevel logic optimizer, which is based on the transduction method, is introduced. The original transduction method is good for optimization, but its calculation time and storage area increase exponentially with the number of inputs because of the use of truth tables. To save CPU time and memory space, the authors implemented this algorithm using ordered binary decision diagrams (OBDD) as the data structure for representing logic functions. Since OBDD does not become as large as other representations, it can handle large circuits without partitioning.<<ETX>>

Variable ordering algorithms for ordered binary decision diagrams and their evaluation

Ordered binary decision diagrams (OBDDs) use restricted decision trees with shared subgraphs. The ordering of variables is fixed throughout an OBDD diagram. However, the size of an OBDD is very sensitive to variable ordering, especially for large circuits. The results of experiments in variable ordering using an experimentally practical algorithm are presented. The algorithm is basically a depth-first traversal through a circuit from the output to the inputs. With this algorithm, circuits having more than 3000 gates and more than 100 inputs can be expressed in reasonable CPU time and with practical memory requirements. >

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N/sup 2/ processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 x 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

On Computing the Transitive Closure of a State Transition Relation

We describe a new, recursive-descent procedure for the computation of the transitive closure of a transition relation. This procedure is the classic binary matrix procedure of [1], adapted to a BDD data structure. We demonstrate its efficacy when compared to standard iterative methods.

LP based cell selection with constraints of timing, area, and power consumption

This paper presents a new LP based optimal cell selection method. Optimal cell selection is a useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle both setup and hold time constraints. We also make an efficient initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it reduces the clock cycle of a manual designed 13k-transistor chip by 17% without any increase of area.

Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.<<ETX>>

A fast state reduction algorithm for incompletely specified finite state machines

This paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a BDD. Experimental results are given to demonstrate that the algorithm described here is faster and obtains better solutions than conventional methods.

A resynthesis approach for network optimization

We resent a new al orithm RENO (Wsynthesis for NetworK Optimization) for the optimization of multi-level combinational networks. In RENO, a given network is minimized for area by optimally resynthesizing each gate, using other existing gates in the network. The resynthesis process is based on a covering-set algorithm, which enables us to resynthesize usin complex gates instead of only simple gates (e.g., NA%D and NOR), thereby exploring more reconfiguration ossibilities. Due to the reconfiguration ability of the R 8 . O algorithm, networks optimized by RENO have good even if no network don’t-care is used. The RE8G!!gorithm has been implemented in both cube and shared-OBDD data structures. Experimental results obtained by RENO for benchmark functions and comparison with the optimization algorithm used in MIS 2.2 show that RENO is very effective for multi-level network optimization.

Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams

Automatic and semi-automatic verification methods for switch-level circuits are presented. Switch-level circuits with no delay (but with/without charge effects) are automatically verified using a formalism with binary decision diagrams (BDD) and temporal logic. Purely bidirectional transistors, such as those whose signal directions are dynamically determined in operations, are treated in the uniform way as nonbidirectional transistors. In the case of switch-level circuits with arbitrary delays, based on the work by M.E. Leeser (1989), the authors present a semi-automatic verification method which uses a propositional theorem prover using BDD. First some assignments of propositional variables to terms of temporal logic are manually given, and then the automatic theorem prover does verification.<<ETX>>