Yusuke Tokunaga

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback

An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented. A voltage-averaging feedback (VAF) concept is proposed to overcome conventional relaxation oscillator problems such as sensitivity to comparator delay, aging, and flicker noise of current sources. A test-chip with typical frequency of 14.0 MHz was fabricated in a 0.18 μm standard CMOS process and measured frequency variations of ±0.16 % for supply changes from 1.7 to 1.9 V and ±0.19% for temperature changes from -40 to 125°C. The prototype draws 25 μA from a 1.8 V supply, occupies 0.04 mm2, and achieves 7x reduction in accumulated jitter (at 1500th cycle) as compared to a oscillator without VAF.

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage

Recently, on-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces such as DDR I/F and HDMI (for initial negotiation), and SoCs. RC oscillators (including relaxation oscillators) were developed to realize on-chip oscillators with standard CMOS processes. In this paper, a power-averaging feedback (PAF) concept for accurate oscillators with low power and small area is presented.

A 69.8 dB SNDR 3 rd -order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver

This paper presents a 3rd-order continuous time delta-sigma modulator for a worldwide digital TV-receiver whose SNDR is 69.8 dB. An ultimate low power tuning system using RC-relaxation oscillator is developed in order to achieve high yield against PVT variations. A 3rd-order modulator with modified single opamp resonator contributes to cost reduction by realizing very compact circuit. The mechanism to occur 2nd-order harmonic distortion at current feedback DAC was analyzed and a reduction scheme of the distortion enabled the modulator to achieved FOM of 0.18 pJ/conv-step.

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization

In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the analog design, including low power and small area, designers have to select an optimal solution among large combination of the following alternatives: which architecture should be adopted; what type of transistors should be taken; and whether digitally assisting technologies should be used or not, etc. A design based on experience and intuition cannot lead to the optimum in a short time. A comprehensive approach to the optimization, based on circuit theory, is now required. Convex optimization procedure can solve the formulae which represent circuit performance with over hundreds of design variables. We have constructed optimization environments for pipelined and delta-sigma analog-to-digital converters (ADCs) in consideration of the digitally assisting techniques and layout constraints. Both 12-bit pipelined ADCs and a 5th-order delta-sigma modulator were designed with the optimizer, and achieved top-ranked power efficiency.

An over 20,000 quality factor on-chip relaxation oscillator using Power Averaging Feedback with a Chopped Amplifier

This paper describes the first achievement of over 20,000 quality factors among on-chip relaxation oscillators. The proposed Power Averaging Feedback with a Chopped Amplifier enables such a high Q which is close to MEMS oscillators. 1/f noise free design and rail-to-rail oscillation result in low phase noise with small area and low power consumption. The proposed oscillator can be applied to low noise applications (e.g. digital audio players) implemented onto a System on a Chip.

A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

A duty-cycle-correcting false-lock-free DLL for DDR interface is proposed. A fully balanced charge-pump equalizes the charge and discharge pulses of the phase detector to reduce update noise. The DLL achieved 49% to 51% duty-cycle output from a 30% to 70% duty-cycle input clock operating from 20 to 300MHz, consumes 9mW from a 2 to 4V supply, and occupies 0.03mm2 in a 0.30mum CMOS process

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution

A current-controlled oscillator (CCO) with 32ps phase resolution is realized by coupling ring oscillators in a 65nm CMOS process. A compact layout method achieves 36times46mum2 area and multiphase outputs whose timing errors are small. A CCO with 63 output phases is used in the PLL for a DVDtimes16 write system. The measured DNL of the output phases is within 1.0LSB at 490MHz

Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application

Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which converts oscillator-output-level to that of power supply, consumes much power; hence, we have devised a new architecture called a multiphase-output level shift system (M-LSs) which has only three transistors in each LS and cuts off short current perfectly. Moreover, we have connected between the adjacent phases of M-LSs with a resistor to improve phase accuracy. The two key techniques mentioned above make power consumption 1/15 of the conventional LS. The PLL consumes about 1 mA at 123 MHz and accomplishes 63-phase accuracy of 0.5LSB.