Akinori Matsumoto

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback

An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented. A voltage-averaging feedback (VAF) concept is proposed to overcome conventional relaxation oscillator problems such as sensitivity to comparator delay, aging, and flicker noise of current sources. A test-chip with typical frequency of 14.0 MHz was fabricated in a 0.18 μm standard CMOS process and measured frequency variations of ±0.16 % for supply changes from 1.7 to 1.9 V and ±0.19% for temperature changes from -40 to 125°C. The prototype draws 25 μA from a 1.8 V supply, occupies 0.04 mm2, and achieves 7x reduction in accumulated jitter (at 1500th cycle) as compared to a oscillator without VAF.

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage

Recently, on-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces such as DDR I/F and HDMI (for initial negotiation), and SoCs. RC oscillators (including relaxation oscillators) were developed to realize on-chip oscillators with standard CMOS processes. In this paper, a power-averaging feedback (PAF) concept for accurate oscillators with low power and small area is presented.

A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks

This paper describes an 8-channel gel-free EEG/electrode-tissue impedance (ETI) acquisition system, consisting of nine active electrodes (AEs) and one back-end (BE) analog signal processor. The AEs amplify the weak EEG signals, while their low output impedance suppresses cable-motion artifacts and 50/60 Hz mains interference. A common-mode feed-forward (CMFF) scheme boosts the CMRR of the AE pairs by 25 dB. The BE post-processes and digitizes the analog outputs of the AEs, it also can configure them via a single-wire pulse width modulation (PWM) protocol. Together, the AEs and BE are capable of recording 8-channel EEG and ETI signals. With EEG recording enabled, ETIs of up to 60 kΩ can be measured, which increases to 550 kΩ when EEG recording is disabled. Each EEG channel has a 1.2 GΩ input impedance (at 20 Hz), 1.75 μVrms (0.5-100 Hz) input-referred noise, 84 dB CMRR and ±250 mV electrode offset rejection capability. The EEG acquisition system was implemented in a standard 0.18 μm CMOS process, and dissipates less than 700 μW from a 1.8 V supply.

A 700µW 8-channel EEG/contact-impedance acquisition system for dry-electrodes

A 700μW 8-channel active-electrode (AE) based EEG monitoring system is presented. The complete system consists of 9 AEs and a back-end analog signal processor. It is capable of continuously recording EEG signals and electrode-tissue contact impedance (ETI). The EEG channels have 1.2GΩ input impedance, 1.75μVrms noise (0.5-100Hz), 84dB CMRR, and can reject ±250mV of electrode offset, while consuming less than <;87μW (including ETI measurement). The system facilitates ambulatory use and patient comfort, while delivering high quality EEG signals.

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization

In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the analog design, including low power and small area, designers have to select an optimal solution among large combination of the following alternatives: which architecture should be adopted; what type of transistors should be taken; and whether digitally assisting technologies should be used or not, etc. A design based on experience and intuition cannot lead to the optimum in a short time. A comprehensive approach to the optimization, based on circuit theory, is now required. Convex optimization procedure can solve the formulae which represent circuit performance with over hundreds of design variables. We have constructed optimization environments for pipelined and delta-sigma analog-to-digital converters (ADCs) in consideration of the digitally assisting techniques and layout constraints. Both 12-bit pipelined ADCs and a 5th-order delta-sigma modulator were designed with the optimizer, and achieved top-ranked power efficiency.

Compact Wireless EEG system with active electrodes for daily healthcare monitoring

Development of Wireless EEG system is described. Realtime impedance monitoring and active electrodes are introduced in order to reduce noise from impedance changes caused due to body motion, and to prevent noise from power line interference, respectively. EEG ASICs are developed for the system. The complete system has a low noise (60nV/√Hz) and is packaged in a compact enclosure (38mm × 38mm × 16mm). The system is evaluated against different types of artefacts and possible applications with the system are discussed.

Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application

Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which converts oscillator-output-level to that of power supply, consumes much power; hence, we have devised a new architecture called a multiphase-output level shift system (M-LSs) which has only three transistors in each LS and cuts off short current perfectly. Moreover, we have connected between the adjacent phases of M-LSs with a resistor to improve phase accuracy. The two key techniques mentioned above make power consumption 1/15 of the conventional LS. The PLL consumes about 1 mA at 123 MHz and accomplishes 63-phase accuracy of 0.5LSB.