Yuta Shiratori

Threshold-variation-enhanced adaptability of response in a nanowire field-effect transistor network

Stochastic resonance in a summing network with varied thresholds was investigated using GaAs-based etched nanowire field-effect transistors having different threshold voltages. The network’s response adapted to input offset fluctuations in the range of the threshold voltage variation and the network could detect a weak signal without any adjustment of the input offset or the addition of high noise. The observed adaptability resulted from a widened dynamic range of the system due to signal decomposition and reconstruction by multiple thresholds together with the output summation process.

Fabrication and characterization of a GaAs-based three-terminal nanowire junction device controlled by double Schottky wrap gates

A three-terminal nanowire junction device controlled by double nanometer-sized Schottky wrap gates (WPGs), which control left and right branches independently, are fabricated utilizing AlGaAs∕GaAs etched nanowires and characterized experimentally. Fabricated device exhibits clear nonlinear characteristics of output voltage at the center terminal by applying voltages to left and right terminals in push-pull fashion. Applying asymmetric gate voltages to left and right WPGs provides clear asymmetry in the output voltage. The nonlinearity in the low voltage regions is greatly enhanced by squeezing both left and right branches using WPGs.

A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology

A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The four-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate control of nanowires. The fabricated circuit integrating 32 node devices exhibits the correct output waveforms at room temperature allowing for threshold voltage variation.

Boolean Logic Gates Utilizing GaAs Three-Branch Nanowire Junctions Controlled by Schottky Wrap Gates

A GaAs-based three-branch nanowire junction (TBJ) with Schottky wrap gates (WPGs) is investigated to realize novel Boolean logic gates. The WPG-controlled TBJ shows a bell-shaped voltage input–output curve and is controlled by gate voltage on the WPGs. The observed characteristics are explained using a simple equivalent circuit model. AND gate operation is realized in the WPG-controlled TBJ and its output voltage swing is controlled using WPGs. It can also operate as a NOT gate by changing the measurement circuit. A NAND gate is fabricated by integrating two WPG-controlled TBJs, and correct operation with a voltage transfer gain of 2.2 is realized.

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannons expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Effect of Size Reduction on Switching Characteristics in GaAs-Based Schottky-Wrap-Gate Quantum Wire Transistors

The effect of size reduction on switching characteristics is investigated experimentally for the low-switching-power operation of GaAs-based quantum wire transistors (QWRTrs) utilizing etched AlGaAs/GaAs nanowires controlled by Schottky wrap gates (WPGs). WPG QWRTrs in which the wire width, W, and gate length, LG, are systematically changed are fabricated and characterized with respect to operation temperature, switching voltage, ΔVG, gate voltage to Fermi energy scaling factor, α, and power-delay product, PDP. When W is less than 200 nm, more than 80% of the fabricated devices exhibit quantized conductance at 30 K. The device with W=40 nm shows a large α of 0.7. Decreasing LG into the sub-100-nm range is found to be effective for improving power consumption, since the short channel effect is suppressed by tight potential control in the WPG structure.

Study on Nonlinear Electrical Characteristics in GaAs-based Three-branch Nanowire Junctions Controlled by Schottky Wrap Gates

Three-branch nanowire junctions (TBJs) have unique nonlinear electrical characteristics based on ballistic transport, which are useful for various logic and analog circuits. However, TBJ devices having rather large dimensions compared with electron mean free path, IF, also show clear nonlinear curves even at room temperature (RT) and the origin has not been clarified yet. In this paper, we investigate a size and temperature dependence of nonlinear electrical characteristics of GaAs-based TBJ devices which have nanometer-sized Schottky wrap gates (WPGs). A simple model was introduced, which could explain experimental data reasonably well.

Characterization of Low-Frequency Noise in Etched GaAs Nanowire Field-Effect Transistors Having SiNx Gate Insulator

Low-frequency noise in SiNx insulator–gate GaAs-based etched nanowire field-effect transistors (FETs) is investigated, focusing on the device size dependence and the effect of electron traps in the insulator. Intensity of the drain current noise is found to systematically increase when the nanowire width and gate length decrease, as indicated by the conventional FET noise model. Noise spectrum also changes continuously from 1/f to 1/f2 with the decrease of the device size, which is not observed in Schottky-gate nanowire FETs. Theoretical analysis shows that traps having short time constants mainly affect on the spectrum slope, whereas those having long time constants only shift the spectrum and do not affect on the slope. Observed size dependence of the spectrum slope is explained by broadening of the distribution of the time constant rather than the change in the combination of discrete traps having different time constants.

Multipath-switching device utilizing a GaAs-based multiterminal nanowire junction with size-controlled dual Schottky wrap gates

A multipath-switching device using a multiterminal nanowire junction with size-controlled dual gates is proposed and demonstrated experimentally. The device switches a number of output terminals according to multiple-valued input voltages for electrons entering from a root terminal. The switching function is implemented by dual gating on multiple nanowires with different threshold voltages Vth. Systematic Vth shift is made by changing gate lengths in nanometer scale. A triple-path-switching device is fabricated using AlGaAs∕GaAs etched nanowires and nanometer-scale Schottky wrap gates. Its correct operation is confirmed at room temperature. Obtained results are explained by a simple analytical model.

Characterization of Low-Frequency Noise in GaAs Nanowire Field-Effect Transistors Controlled by Schottky Wrap Gate

Low-frequency noise in GaAs-based nanowire field-effect transistors (FETs) controlled by a Schottky wrap gate (WPG) is investigated focusing on the size dependence of 1/f noise and the basic behavior of a gentle slope of the noise spectrum at a relatively high frequency. 1/f noise is found to systematically depend on the nanowire width W and gate length LG, which is explained by the conventional flicker noise model. The evaluated flicker noise coefficient KF is on the order of 10-23 V2 F, comparable to that of Si metal–oxide–semiconductor (MOS) FETs. The gentle slope close to 1/f0.5 frequently appears in the noise spectrum from the fabricated devices. Its intensity is found to be proportional to gate leakage current, suggesting that electrons flowing through the AlGaAs barrier layer induce generation-recombination (GR) noise in the gate region.