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Dive into the research topics where Kensuke Miura is active.

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Featured researches published by Kensuke Miura.


Applied Physics Letters | 2010

Threshold-variation-enhanced adaptability of response in a nanowire field-effect transistor network

Seiya Kasai; Kensuke Miura; Yuta Shiratori

Stochastic resonance in a summing network with varied thresholds was investigated using GaAs-based etched nanowire field-effect transistors having different threshold voltages. The network’s response adapted to input offset fluctuations in the range of the threshold voltage variation and the network could detect a weak signal without any adjustment of the input offset or the addition of high noise. The observed adaptability resulted from a widened dynamic range of the system due to signal decomposition and reconstruction by multiple thresholds together with the output summation process.


Applied Physics Express | 2010

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

Yuta Shiratori; Kensuke Miura; Rui Jia; Nanjian Wu; Seiya Kasai

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannons expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.


Japanese Journal of Applied Physics | 2012

Characterization of Low-Frequency Noise in Etched GaAs Nanowire Field-Effect Transistors Having SiNx Gate Insulator

Toru Muramatsu; Kensuke Miura; Yuta Shiratori; Zenji Yatabe; Seiya Kasai

Low-frequency noise in SiNx insulator–gate GaAs-based etched nanowire field-effect transistors (FETs) is investigated, focusing on the device size dependence and the effect of electron traps in the insulator. Intensity of the drain current noise is found to systematically increase when the nanowire width and gate length decrease, as indicated by the conventional FET noise model. Noise spectrum also changes continuously from 1/f to 1/f2 with the decrease of the device size, which is not observed in Schottky-gate nanowire FETs. Theoretical analysis shows that traps having short time constants mainly affect on the spectrum slope, whereas those having long time constants only shift the spectrum and do not affect on the slope. Observed size dependence of the spectrum slope is explained by broadening of the distribution of the time constant rather than the change in the combination of discrete traps having different time constants.


Japanese Journal of Applied Physics | 2011

Characterization of Low-Frequency Noise in GaAs Nanowire Field-Effect Transistors Controlled by Schottky Wrap Gate

Kensuke Miura; Yuta Shiratori; Seiya Kasai

Low-frequency noise in GaAs-based nanowire field-effect transistors (FETs) controlled by a Schottky wrap gate (WPG) is investigated focusing on the size dependence of 1/f noise and the basic behavior of a gentle slope of the noise spectrum at a relatively high frequency. 1/f noise is found to systematically depend on the nanowire width W and gate length LG, which is explained by the conventional flicker noise model. The evaluated flicker noise coefficient KF is on the order of 10-23 V2 F, comparable to that of Si metal–oxide–semiconductor (MOS) FETs. The gentle slope close to 1/f0.5 frequently appears in the noise spectrum from the fabricated devices. Its intensity is found to be proportional to gate leakage current, suggesting that electrons flowing through the AlGaAs barrier layer induce generation-recombination (GR) noise in the gate region.


international symposium on multiple-valued logic | 2009

Multi-path Switching Device Utilizing a Multi-terminal Nanowire Junction for MDD-Based Logic Circuit

Seiya Kasai; Yuta Shiratori; Kensuke Miura; Nanjian Wu

Simple and compact multi-path switching devices for multi-valued decision diagram (MDD)-based logic circuits are designed, fabricated and characterized. The devices switch multiple exit branches for electrons entering from an entry branch, according to multi-valued input. The switching function is implemented by dual gating on multiple nanowires with different threshold voltages. The gate threshold voltage is controlled by precise design of gate structures and sizes in nanometer scale. The operation principle of the device is described using a simple analytical model. Ternary-path switching devices are demonstrated using AlGaAs/GaAs etched nanowire junctions together with nanometer-scale Schottky wrap gates (WPGs) and in-plane gates (IPGs).


Physica Status Solidi (c) | 2011

Control of stochastic resonance response in a GaAs‐based nanowire field‐effect transistor

Seiya Kasai; Yuta Shiratori; Kensuke Miura; Yuta Nakano; Toru Muramatsu


Microelectronic Engineering | 2011

Programmable nano-switch array using SiN/GaAs interface traps on a GaAs nanowire network for reconfigurable BDD logic circuits

Yuta Shiratori; Kensuke Miura; Seiya Kasai


Technical report of IEICE. SDM | 2011

Fabrication of GaAs-based Nanowire CCD Controlled by Schottky Wrap Gates and Characterization of Its Charge Transfer Operation

Yuki Nakano; Kensuke Miura; Yuta Shiratori; Seiya Kasai


IEICE technical report. Electron devices | 2011

Characterization of Low-Frequency Noise in SiN_x Insulator-Gate GaAs Etched Nanowire FETs

Toru Muramatsu; Kensuke Miura; Yuta Shiratori; Seiya Kasai


OECC 2010 Technical Digest | 2010

THz wave detection by gate-controlled GaAs nanowire devices

Seiya Kasai; Yuta Shiratori; Kensuke Miura; Hiromu Shibata; Y. Nakano; Toru Muramatsu

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Nanjian Wu

Chinese Academy of Sciences

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Rui Jia

Chinese Academy of Sciences

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