Yutaka Arita

A 500 MHz pipelined burst SRAM with improved SER immunity

One of the components key to increased mobile computer performance is level-2 (L2) cache memory, which is usually a high-frequency synchronous SRAM and typically consumes >2 W. This SRAM has to be housed in low-thermal-resistance package such as the plastic ball grid array (PBGA). Power dissipation must be reduced, since battery life is prolonged and a lower-cost TQFP package can be used. In addition, cosmic-ray-induced single soft errors are becoming a problem, since memory cell node capacitance is reduced with reduction of memory cell size. At high altitude (air flight level of 30000 ft), cosmic-ray-induced SER is increased by 2 orders of magnitude. This type of soft error is significant for mobile applications. The 64k x 36 synchronous pipelined burst SRAM (PBSRAM) described has lower power and improved SER immunity.

Experimental Investigation of Thermal Neutron-Induced Single Event Upset in Static Random Access Memories

Static random access memories (SRAMs) with a borophosphosilicate glass film (BPSG) and with a normal silicon oxide film (non-boron-doped silicon oxide film) were fabricated, and the influence of a BPSG film on the neutron-induced single event upsets (SEUs) was investigated. It was confirmed that the thermal neutron reactions on boron atoms in a BPSG film induce SEUs. The SEU rate depends strongly on cell charge and increases as the cell charge decreases. In future SRAMs with a small cell size and low operating voltage, the thermal neutron reaction on boron atoms in a BPSG film will play a significant role to the neutron-induced single event upsets.

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell

Low-voltage SRAMs operating at <3 V are currently used for handy terminals. However, demand for lower-voltage operation has increased. It is difficult to reduce operating voltage below 2.5 V with a conventional low-power SRAM with 4-nMOS-transistor cell. Although a full CMOS cell or a boosted word line technique could reduce operating voltage, they have certain problems, i.e., a larger cell or elaborate timing control for boost. This 256 kb, low-power SRAM uses a bipolar bit line contact (BBC) memory cell, and features small cell, low operating voltage, low power dissipation and fast access.

Influence of Elastic Scattering on the Neutron-Induced Single-Event Upsets in a Static Random Access Memory

Neutron single-event upsets (SEUs) induced by elastic scattering were investigated by an experiment using 2 MeV neutron beams and by a calculation based on scattering cross-section data and angular distribution data from the evaluated nuclear data file (ENDF). The SEU rates obtained by the calculation and experiment are in fairly good agreement if the region sensitive to the SEUs (sensitive volume) is properly defined. Adopting the calculation to atmospheric neutrons, the fraction of the SEU rates induced by elastic scattering accounted for approximately 26 to 32% of the total fast-neutron-induced SEUs in the atmospheric neutron environment. Reducing well depth will effectively reduce the number of SEUs.

Evaluation of Fast Neutron Induced Single Event Upset in a Static Random Access Memory and Simulation by Monte Carlo N-Particle Code (MCNPX)

Neutron-induced single-event upsets (SEUs) in a 0.4 µm 4 Mbit CMOS SRAM (complimentary metal oxide semiconductor static random access memory) were investigated using high-energy neutron beams and Monte Carlo simulation by MCNPX (Monte Carlo N-Particle Code). The Monte Carlo simulation, based on the assumption that the primary cause of SEUs is alpha particles generated by nuclear fission, agreed with the experimental results within the accuracy of ±29% in the case of small cell charges (<10 fC). When the devices were exposed to fast neutrons in the front-surface direction, the SEU rates increased by a factor of 1.1 to 2 in comparison with the case of back-surface irradiation. According to the Monte Carlo simulation, the difference between the alpha particle production cross section of the carbon atom in package materials and that of the silicon atom caused this phenomenon.

Single Event Upset in Static Random Access Memories in Atmospheric Neutron Environments

Single-event upsets (SEUs) in a 0.4 ?m 4 Mbit complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) were investigated in various atmospheric neutron environments at sea level, at an altitude of 2612 m mountain, at an altitude of commercial airplane, and at an underground depth of 476 m. Neutron-induced SEUs increase with the increase in altitude. For a device with a borophosphosilicate glass (BPSG) film, SEU rates induced by thermal neutrons increase with the decrease in the cell charge of a memory cell. A thermal neutron-induced SEU is significant in SRAMs with a small cell charge. With the conditions of small cell charge, thermal neutron-induced SEUs account for 60% or more of the total neutron-induced SEUs. The SEU rate induced by atmospheric thermal neutrons can be estimated by an acceleration test using 252Cf.

Simulation of Thermal-Neutron-Induced Single-Event Upset Using Particle and Heavy-Ion Transport Code System

The simulation of a thermal-neutron-induced single-event upset (SEU) was performed on a 0.4-µm-design-rule 4 Mbit static random access memory (SRAM) using particle and heavy-ion transport code system (PHITS). The SEU rates obtained by the simulation were in very good agreement with the result of experiments. PHITS is a useful tool for simulating SEUs in semiconductor devices. To further improve the accuracy of the simulation, additional methods for tallying the energy deposition are required for PHITS.