Tomohisa Wada

A 14-ns 1-Mbit CMOS SRAM with variable bit organization

THE MEMORY CAPACITY OF SRAMs have quadrupled over the past three years. In ’87, several 1Mb SRAMs whose access times were more than 25ns have been r e p ~ r t e d ~ ” ’ ~ ’ ~ . However, access time below 25ns is necessary, expecially for high-performance computer systems. Fast SRAMs, usually organized in x 1 or x 4, are fabricated by exchanging the A1 layer mask5. But, high-density SRAMs face extended testing time, as in DRAMs. This report will describe a 1Mb CMOS SRAM with a 14ns access time and a variable bit-organization function, whereby a lMbx1 RAM can be changed to 256Kx4, t o reduce testing time. To shorten the access time we need a fast word line selection, a highly sensitive sense amplifier, rapid data transfer from a sense amplifier t o a data output buffer, and a small delay time in the data output buffer. To minimize word line selection time, a small word line CR-delay, high speed decoding-and powerful word line driver are indispensable. Figure 1 shows a block diagram of the RAM, where the 1Mb memory cell array consists of 512 rows and 2048 columns, which is divided into 32 blocks. Each block includes 512 rows and 6 4 columns with one redundant column. The word line is formed by the polycide with a sheet resistance of 5s2 /square. This short and low-resistivity word line structure reduces the word line delay time to 0.5ns. Address signals are split into four groups (X, Y, Z and W). The X-, Y-, Zand Waddress signals are uscd for the selection of row, column, block and sense amplifier, respectively. The W-address is used only in l M b x l organization. Figure 2 shows the word-line selection circuit. The divided word line architecture is adopted6. The block row decoder is composed of a NAND-gate and a CMOS inverter. This two-stage decoder gives an expanded word-line drivability.

A 500 MHz pipelined burst SRAM with improved SER immunity

One of the components key to increased mobile computer performance is level-2 (L2) cache memory, which is usually a high-frequency synchronous SRAM and typically consumes >2 W. This SRAM has to be housed in low-thermal-resistance package such as the plastic ball grid array (PBGA). Power dissipation must be reduced, since battery life is prolonged and a lower-cost TQFP package can be used. In addition, cosmic-ray-induced single soft errors are becoming a problem, since memory cell node capacitance is reduced with reduction of memory cell size. At high altitude (air flight level of 30000 ft), cosmic-ray-induced SER is increased by 2 orders of magnitude. This type of soft error is significant for mobile applications. The 64k x 36 synchronous pipelined burst SRAM (PBSRAM) described has lower power and improved SER immunity.

Simple noise model and low-noise data-output buffer for ultrahigh-speed memories

An analytic noise (voltage bounce on chip-internal V/sub CC//GND lines) model for data-output buffers is described. The model indicates that t/sub r/ (switching time of output transistor) greater than L*G/sub 0/ (product between the parasitic inductance on V/sub CC//GND lines and the conductance of the output transistor) and small output voltage amplitude are required in order to reduce the noise voltage. The model give VLSI circuit designers a rough estimation of the V/sub CC//CND line noise. A low-noise data-output buffer combined with a voltage down converter (VDC) is proposed. It decreases the peak noise voltage by one-half without degrading the access time. >

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 mu m CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V. >

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8- mu m BiCMOS technology. >

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

The authors propose a novel bit line architecture, the T-shaped bit line architecture (TSBA), which is suitable for high-speed, high-density and/or large bit-wide configuration SRAMs (static random-access memories). This architecture is applied to 256-kb BiCMOS TTL (transistor-transistor logic) I/O SRAM with a typical access time of 5.8 ns. To achieve sub-6-ns access time, a bipolar Darlington column sense amplifier, a global column decode technique, a shielded data bus technique with TSBA, and 0.8- mu m BiCMOS technology are employed.<<ETX>>

Variable bit organization as a new test function for standard memories

A variable bit-organization function that enables the RAM to be used in plural bit organizations is proposed. This function reduces the test time for many kinds of test patterns and data patterns. Consequently, a short-time, accurate, and severe test is realized. This test-time reduction function is important in a high-speed memory such as SRAM because it preserves the same access time for the different organizations. Using the output driver transistor as the input protection circuit, a low and uniform input/output pin capacitance of 3.5 pF and a high electrostatic discharge (ESD) immunity have also been realized. This function has been successfully implemented in a 1-Mb SRAM configurable for both 1-M-word*1-b and 256K-word*4-b organizations without any practical drawbacks. >