Kazuhito Tsutsumi

A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture

A 20-ns, 4-Mb CMOS SRAM with both 4 M*1 and 1M*4 organizations and fabricated using a quadruple-polysilicon, double-metal, twin-well 0.6- mu m CMOS process technology is described. A word-decoding architecture and a sensitive sense amplifier, combined with an address transition detector (ATD) technique, realize high-speed, low-power operation. Because conventional divided-word-line (DWL) structure cannot realize the high-speed and low-power word decoding in megabit SRAMs, hierarchical word decoding (HWD) is utilized. The RAM has a fast address mode using the 16-b parallel data bus scheme.<<ETX>>

A C-switch cell for low-voltage and high-density SRAMs

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of /spl mu/A order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 /spl mu/m design rules.

A 21-mW 4-Mb CMOS SRAM for battery operation

The authors describe a 21-mW 4-mB CMOS SRAM for the application of memory systems which operate on 3-V batteries. A low active power is achieved by novel circuit technologies. A thin-film transistor (TFT) load memory cell effectively reduces standby current to 0.4 mu A. A new multibit test circuit, which permits measurement of access time, is also introduced for a reduction of the test time. The authors describe the characteristics of the TFT memory cell and the improved memory cell design for stable cell operation. The 0.6- mu m process technology used to fabricate the 4-Mb SRAM and the chip performance are outlined. >

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-/spl mu/m design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT.

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell

Low-voltage SRAMs operating at <3 V are currently used for handy terminals. However, demand for lower-voltage operation has increased. It is difficult to reduce operating voltage below 2.5 V with a conventional low-power SRAM with 4-nMOS-transistor cell. Although a full CMOS cell or a boosted word line technique could reduce operating voltage, they have certain problems, i.e., a larger cell or elaborate timing control for boost. This 256 kb, low-power SRAM uses a bipolar bit line contact (BBC) memory cell, and features small cell, low operating voltage, low power dissipation and fast access.

Cornerless active area cell and Bi-T-MOS process for sub-half micron SRAMs

This paper presents a novel memory cell and process technology. The memory cell adopts the symmetry layout which has cornerless active area, a single bent word line and common gate TFTs. Furthermore, this memory cell realizes large cell ratio using a direct contact off-set resistance. The proposed process technology is optimization of bipolar, TFT and CMOS process (Bi-T-MOS). The Bi-T-MOS technology decreases the poly-silicon layers to triple-level without decreasing performance of the transistors.<<ETX>>