Yuuichi Takeuchi

SiC Migration Enhanced Embedded Epitaxial (ME3) Growth Technology

In this work, we have developed an innovative epitaxial growth process named the “Migration Enhanced Embedded Epitaxial” (ME3) growth process. It was found that at elevated growth temperatures, the epitaxial growth at the bottom of the trenches is greatly enhanced compared to growth on the sidewalls. This is attributed to the large surface diffusion length of reactant species mainly due to the higher growth temperature. In addition, it was found that this high temperature ME3 growth process is not influenced by the crystal-orientation. Similar growth behavior was observed for stripe-trench structures aligned either along the [11-20] or [1-100] directions. No difference was observed in the electrical performance of the pn diodes fabricated on either oriented stripe geometry. The ME3 process can also be used as an alternative to ion-implantation technology for selective doping process.

In Situ Nitrogen and Aluminum Doping in Migration Enhanced Embedded Epitaxial Growth of 4H-SiC

The in-situ doping of aluminum and nitrogen in migration enhanced embedded epitaxy (ME3) is investigated with the aim to apply it to the realization and fabrication of all-epitaxial, normally-off 4H-SiC JFET devices. This ME3 process consists of the epitaxial growth of an n-doped channel and a highly p-doped top gate in narrow trenches. We found that the nitrogen doping in the n-channel (a-face) is a factor 1.5 higher than layers grown with the same process on Si-face wafers. Due to the low C/Si ratio and the low silane flow rate used in the ME3 process, the growth of the p-doped top gate needs high flow rates of the aluminum precursor trimethylaluminum for several hours, which contaminates the CVD reactor and causes aluminum memory effects. These aluminum memory effects can be reduced by an extra high temperature bake-out run.

Growth Mechanism and 2D Aluminum Dopant Distribution of Embedded Trench 4H-SiC Region

The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the combined analysis of secondary ion mass spectrometry (SIMS) and scanning spreading resistance microscopy (SSRM) results. The maximum variation of Al concentration in the trench is estimated to be about 4-times, which suggests that the Al concentration is highest for the (0001) plane and lowest for the trench corner (1-10x) plane. Al concentration in the (1-100) plane, which determines the JFET p-gate doping level is 1.5-times lower than (0001) plane for trench region fabricated on Si-face wafers.

Homoepitaxial Growth of 4H-SiC on Trenched Substrates by Chemical Vapor Deposition

We have studied the homoepitaxial growth of SiC by CVD on trenched 8° off-axis 4H-SiC (0001) substrates formed by reactive ion etching (RIE). The influences of C/Si ratio and trench direction on the growth have been investigated. Growth near the trenches perpendicular to the off-direction tended to be highly asymmetric due to the influence of step-flow growth, and the (0001) facet was formed at the downstream sides of off-direction. In contrast, growth near the trenches parallel to the off-direction was symmetric. Although the growth rate on the trench sidewall is usually lower than that on the bottom of the trench and top surface, this difference in the epilayer thickness becomes smaller with decreasing C/Si ratio during growth.

Switching Performance of Epitaxially Grown Normally-Off 4H-SiC JFET

Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.

Evaluation of Termination Techniques for 4H-SiC Pin Diodes and Trench JFETs

An investigation concerning suitable termination techniques for 4H-SiC trench JFETs is presented. Field plates, p+ floating rings and junction termination extension techniques are used to terminate 1.2kV class PiN diodes. The fabricated PiN diodes evaluated here have a similar design to trench JFETs. Therefore, the conclusions for PiN diodes can be applied to JFET structures as well. Numerical simulations are also used to illustrate the effect of the terminations on the diodes’ blocking mode behaviour.

150mm Silicon carbide selective embedded epitaxial growth technology by CVD

In this work, we have developed a selective embedded epitaxial growth process on 150-mm-diameter wafer by vertical type hot wall CVD reactor with the aim to realize the all-epitaxial 4H-SiC MOSFETs [1, 2, 3, 4, 5]. We found that at elevated temperature and adding HCl, the epitaxial growth rate at the bottom of trench is greatly enhanced compare to growth on the mesa top. And we obtain high growth rate 7.6μm/h at trench bottom on 150mm-diameter-wafer uniformly with high speed rotation (1000rpm).

3D Raman Spectroscopy Investigation of Defects in 4H-SiC Epilayer

In this report we were able to successfully identify and localize in 3D 3C and 6H foreign polytypes and stress in the embedded epilayer by high resolution 3D Raman spectroscopy, that were otherwise invisible under the microscope or SEM, in non-contact and non-destructive way. Stripe patterned deep trenches with aspect ratio about 2 (depth=3.0μm; width=1.5μm) were formed on 4H-SiC substrate by ICP. The epitaxial layer was embedded in these trenches by SiC CVD. Poly type defects and stress in the embedded epilayer were mapped by curve-fitting of spectra obtained from Raman measurement of the embedded SiC epilayer. The location of the foreign polytypes and the stress inside the stripe pattern allows speculating on the origin of the defects and correlating it to the manufacturing process.

Fabrication of a SiC Double Gate Vertical Channel JFET and It's Application in Power Electronics

The fabrication process of an innovative epitaxial trench JFET with vertical channel and double gate control is reviewed. Due to the excellent doping and thickness control of the epitaxial regrowth techniques, the sub-micron channel can be tailored for normally-on and -off operation. Due to the vertical channel design the epitaxial trench JFETs have narrow cell pitch for high-density power integration and high saturation current capabilities. The excellent performance of these fabricated and packaged JFET devices is demonstrated with on-wafer measurements and power switching tests. High current conduction tests are performed at room temperature and elevated temperatures of 125°C with switching frequencies of 30 kHz and 200 kHz.

High temperature direct double side cooled inverter module for hybrid electric vehicle application

In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, doublesided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.