Yuuki Enatsu

OG-FET: An In-Situ

In this letter, a novel device design to achieve both low ON-resistance and enhancement mode operation in a vertical GaN FET is demonstrated. In the traditional trench MOSFET structure, a dielectric is deposited on an n-p-n trenched structure and the channel forms via p-GaN inversion at the dielectric/p-GaN interface. However, this results in a relatively high ON-resistance due to poor electron mobility in the channel. By changing the structure to include a metal-organic chemical vapor deposition (MOCVD)-regrown Un-intentionally Doped (UID)-GaN interlayer followed by an in-situ dielectric (MOCVD Al2O3) cap on the n-p-n trenched structure, a pathway (channel) for enhanced electron mobility is created, resulting in reduced ON-resistance. Preliminary results for this device design demonstrated almost 60% reduction in the ON-resistance and similar breakdown voltage compared with a traditional trench MOSFET structure while maintaining normally off operation with a threshold voltage of 2 V.

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GaN is one of the best suited materials for high-power devices due to its superior material properties such as high breakdown field, wide band gap and high saturation drift velocity. Consequently, GaN power devices have gained increased attention in recent years. Numerous vertical GaN power transistors have been demonstrated in the past few years [1-4]. One of the preferred GaN vertical device designs is the trench MOSFET. In the traditional trench MOSFET structure [2-4], the channel forms via p-GaN inversion at the dielectric/p-GaN interface resulting in a relatively high on-resistance due to the poor electron mobility in the channel. In this work, we present a novel device design to lower the on-resistance in a trench MOSFET. By inserting a MOCVD regrown GaN interlayer prior to the dielectric deposition (MOCVD Al2O3) on the trenched structure, lower on-resistance is achieved due to enhancement in the electron mobility of the channel. For an optimal GaN interlayer thickness of 10 nm, a low on-resistance (active area) of 0.97 mΩ.cm2 alongside enhancement mode operation (Vth = 3 V) is demonstrated.

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GaN trench-gate MOSFETs with m- and a-plane-oriented sidewall channels were fabricated and characterized. The trench-gate MOSFET performance depended strongly on the sidewall-MOS-channel plane orientation. The m-plane-oriented MOS channel devices demonstrated higher channel mobility, higher current density, lower sub-threshold slope, and lower hysteresis with similar threshold voltage and on–off ratio compared to a-plane MOS channel devices. These results indicate that orienting trench-gate MOSFET toward the m-plane would allow for better on-state characteristics while maintaining similar off-state characteristics.

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Controlled n-type doping down to 2 × 1015 cm−3 was achieved in GaN grown on sapphire by MOCVD by balancing the n-type Si doping with respect to the background carbon and oxygen levels. A dopant level of ~1 × 1016 cm−3 displayed a very high mobility of 899 cm2 V−1 s−1. High electron mobility in the drift layer leads to a low on resistance and high current densities without compromising on any other properties of the device. Schottky diodes processed on these low n-type layers showed low R on values, while the p–n diodes display high reverse breakdown voltages in excess of 1000 V for 8 μm thick drift layers with a doping of 2 × 1015 cm−3.

aN Interlayer-Based Vertical Trench MOSFET

A polarization-induced three-dimensional hole gas (3DHG) was demonstrated in undoped and compositionally graded In x Ga1− x N layers. All samples were grown on Ga-face bulk GaN substrates by metal organic chemical vapor deposition. A high hole concentration of 2.8 × 1018 cm−3 was obtained in a 100-nm-thick In x Ga1− x N layer where the indium composition was graded from x = 0 to x = 0.2. 3DHG density control by varying the indium composition and thickness of a compositionally graded In x Ga1− x N layer was also demonstrated.