Yvan Eustache

Closed-loop--based self-adaptive Hardware/Software-Embedded systems: Design methodology and smart cam case study

This article presents our methodology for implementing self-adaptivness within an OS-based and reconfigurable embedded system according to objectives such as quality of service, performance, or power consumption. We detail our approach to separate application-specific decisions and hardware/software-implementation decisions at system level. The former are related to the efficiency control of applications and based on the knowledge of application engineers. The latter are generic and address the choice between various hardware and software implementations according to user objectives. The decision management is implemented as an adaptive closed-loop model. We describe how each design step may be implemented and especially how we solved the issue of stability. Finally, we present a video-tracking application implemented on a FPGA to demonstrate the effectiveness of our solution, results are given for a system built around a NIOS soft-core with μCOS II RTOS and new services for managing hardware and software tasks transparently.

Specification and OS-based implementation of self-adaptive, hardware/software embedded systems

This paper presents our solution for specifying and implementing self-adaptivness within an OS-based and reconfigurable embedded system according to objectives such as quality of service (QoS), performance or power consumption. More precisely, we detail our approach to separate, at runtime, application-specific decisions and hardware/software implementation decisions at system level. The first ones are related to the control of the efficiency of applications, they are specified in Local Configuration Managers (LCM) based on the knowledge of application engineers. The second ones are generic and address the choice between various hardware and software implementations according to observations of the gap between online measurements and objectives set by the user, these decisions are implemented in the Global Configuration Manager (GCM) as an adaptive close-loop model. We have designed a video tracking application on an FPGA to demonstrate the effectiveness of our solution, results are given for a system built around a NIOS soft-core with ¼COS II RTOS and new services for managing hardware and soft-ware tasks transparently.

Reconfiguration Management in the Context of RTOS-Based HW/SW Embedded Systems

This paper presents a safe and efficient solution to manage asynchronous configurations of dynamically reconfigurable systems-on-chip. We first define our unified RTOS-based framework for HW/SW task communication and configuration management. Then three issues are discussed and solutions are given: the formalization of configuration space modeling including its different dimensions, the synchronization of configuration that mainly addresses the question of task configuration ordering, and the configuration coherency that solves the way a task accepts a new configuration. Finally, we present the global method and give some implementation figures from a smart camera case study.

Design and implementation of a near maximum likelihood decoder for Cortex codes

Cortex codes are an emerging family among the rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient Maximum Likelihood (ML) decoder for Cortex codes. It first reviews a dedicated architecture that takes advantage of the particular structure of this code to simplify the decoding. Then, we propose a technique to improve the architecture by the generation of an optimal list of binary vectors. An optimal stopping criterion is also proposed. Simulation results show that the proposed architecture achieves an excellent performance/complexity trade-off for short Cortex codes. The proposed decoder architecture has been implemented on an FPGA device for the (24,12,8) Cortex code. This implementation supports an information throughput of 300 Mb/s. At a signal-to-noise ratio Eb/No=8 dB, the Bit Error Rate equals 2 × 10-10, which is close to the performance of the Maximum Likelihood decoder.

Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration

Nowadays, the development, maintenance and evolution of products based on FPGAs remains a difficult and time consuming task, especially in todays stringent and fast-paced markets. Designers need to master technology-specific implementation details, which often vary across FPGA models, tool versions and vendors, thus making it difficult to port code from one target device to another. To address these problems, we present the Kaolin model-based development process and tool. Kaolin users design their systems at the functional level, whilst the execution platform-specific details are automatically generated according to the selected FPGA platform model. Additionally, legacy HDL code can be imported thanks to state-of-the-art bi-directional model transformations, so that existing systems can be retargeted to other FPGA platforms. The advantages of Kaolin are demonstrated via an industrial acoustic recorder case study, which has been automatically imported into Kaolin and retargeted to a different FPGA platform with improved performances.

RTOS extensions for dynamic hardware / software monitoring and configuration management

We present our solution for a flexible and unified implementation of self-adaptive systems on reconfigurable architectures. This approach is based on a couple of local and global reconfiguration managers. In this paper we describe how the managers are implemented in the context of an usual RTOS and the new services we add for hardware and software monitoring, reconfiguration decision and reconfiguration control which also includes hardware and software interface modeling.

Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms

In this demo we will present a design flow for multi-core based embedded systems. Namely, we implement a kernel capable of modifying the system at run time to increase data throughput. The design flow starts with the Dynamic Dataflow and RVC-CAL (Reconfigurable Video Coding Cal Actor Language) descriptions of an application and goes up to the deployment of the system onto the hardware platform. As a use case, we implement an MPEG-4 decoder algorithm onto a multi-core heterogeneous system deployed onto the Zynq platform from Xilinx.

Configuration Management in the Context of Self Adaptive Systems

This paper presents a solution to safely and efficiently manage configurations of dynamically reconfigurable system on chip. We first define our unified RTOS-based framework for HW/SW task communication and configuration management. Then three issues are discussed and solutions given: the formalization of configuration space modeling including its different dimensions, the synchronization of configuration that mainly addresses the issue of task configuration ordering and the configuration coherency that solve the control the way a task accepts a new configuration. Finally we present the global method and give some implementation figures from a smart camera case study.