Yves Joannon

Behavioral modeling of WCDMA transceiver with VHDL-AMS language

This article presents the behavioral modeling of a WCDMA transceiver. The model has been developed in VHDL-AMS language. The WCDMA behavioral model is made of RF parameters like gain, impedance, IIP, leakages. The methodology used to develop this model is included in a top-down design flow. The model has been validated by the comparisons between simulation results and measurements on a silicon prototype

Choice of a high-level fault model for the optimization of validation test set reused for manufacturing test

With the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.

Decreasing Test Qualification Time in AMS and RF Systems

The authors of this article illustrate a means to use design models and simulation testbenches to decrease manufacturing test costs. This technique enables test cost optimization early in the RFIC design phase. In this article, we propose a test set optimization and qualification method that targets test application time, cost, and quality while also decreasing the generation time of production tests. Our approach decreases the manufacturing test cost of AMS and RF SoCs by automatically qualifying and optimizing existing test sets. We present a computer-aided test (CAT) tool, Plasma (platform for system qualification with mixed and analog signals), that uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. Our approach relies on the qualification and optimization of a predefined test set. With this article, we show how to reduce the test optimization time by using behavioral modeling and decreasing the number of simulated circuits. This method reduces the number of simulated fault-free models, thanks to a normal estimation.

Qualification of behavioral level design validation for AMS & RF SoCs

The expansion of Wireless Systems-on-Chip leads to a rapid development of design and manufacturing methods In this paper, the test vectors used for design validation of AMS & RF SoCs are evaluated and optimized. This qualification is based on a fault injection method. A fault model based on variation of behavioral parameters and a related qualification metric are proposed. This approach is used in the receiver’s design of a WCDMA transceiver. A test set defined by verification engineers during the validation of this system is qualified and optimized. Then, this test set is compared with a second test set automatically generated by a developed tool.