Z. A. Noor Faizah

Statistical process modelling for 32nm high-K/metal gate PMOS device

The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moores Law. In this paper, the design, fabrication and characterization of 32nm HfO₂/TiSi₂ PMOS device is presented; replacing the conventional SiO₂ dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (V_TH) and leakage current (I_OFF). The simulation result shows that the optimal value of V_TH and I_OFF which are 0.1030075V and 3.4264075×10^-12A/um respectively are well within ITRS prediction.

Modeling of 14 nm gate length n-Type MOSFET

Metal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moores Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and devices characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922×10-6 A/um and 77.11×10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm devices gate length utilizing High-K/Metal Gate n-type MOSFET in impending work.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate a...

Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method

This paper aims to study the effect of process parameter variation on a nano-scaled planar p-type MOSFET (metal-oxide-semiconductor field-effect transistor) device for 22 nm technology using Taguchis L9 orthogonal array. The device was constructed with high-k/metal gate consisting of Titanium dioxide (TiO2) and Tungsten silicide (WSix) metal gate using an industrial-based numerical simulator. Using Taguchis Signal-to-noise ratio (SNR) of nominal-the-best (NTB), the compensation implantation has been as identified as the dominant factor influencing the Vth value with 67.77% while the Halo implantation tilting angle has been identified as the adjustment factor. Upon optimization, the Vth value is -0.29538 V which is within the requirements of the International Technology Roadmap for Semiconductors (ITRS) 2012 which is -0.289 V ± 12.7 %.

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.