Z.J. Li

An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

An output capacitor-free low-dropout regulator (LDO) using a class-AB operational amplifier and an assistant push–pull output stage (APPOS) circuit to enable fast-transient response with ultralow-power dissipation is presented in this brief. The APPOS circuit is proposed to deliver an extra current that is directly proportional to the output current of the class-AB operational amplifier during transient state with an automatic on/off feature. Moreover, the small-signal and large-signal responses of LDO can be separately optimized. As a result, transient performances of LDO are improved significantly without requiring an area-consuming on-chip capacitor anymore. The proposed LDO has been implemented in a standard 0.35-<formula formulatype=inline><tex Notation=TeX>

An enhanced double current limit technique used in high power BUCK converter

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A novel E-SIMOX high voltage device structure with the charge islands on the SOI

</tex></formula> CMOS process. Experimental results show that the LDO can regulate the output voltage at 1.0 V from a 1.2-V supply voltage for the maximum load current of 100 mA. The output voltage fully recovers within 2.7 <formula formulatype=inline><tex Notation=TeX>

Fast speed lateral IGBT with Buried N-region Controlled Anode on SOI substrate

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Analysis of back-gate effect on breakdown behaviour of over 600V SOI LDMOS transistors

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SOI high-voltage device with step thickness sustained voltage layer

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SJ-LDMOS with high breakdown voltage and ultra-low on-resistance

</tex></formula> to 100 mA at a 1.2-<formula formulatype=inline> <tex Notation=TeX>

SOI SJ high voltage device with linear variable doping interface thin silicon layer

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Simulation of high-power 4H-SiC MESFETs with 3D tri-gate structure

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High voltage SOI SJ-LDMOS with dynamic back-gate voltage

An enhanced double current limit technique suitable for high power buck converter is presented in this paper to protect the converter from damage under any fault condition. The first peak current limit circuit works properly when the output is in minor over load. If the current increases continuously to some amount after the first peak current limit working in major overload or short circuit, the frequency of the BUCK converter is decreased by the second peak current limit circuit. The duty cycle can decrease below the value normally limited by the propagation delay in this way. The enhanced current limit technique has been validated with UMC 0.6-µm BCD process based on a monolithic voltage-mode BUCK converter capable of driving up to 3A loads with supply voltage from 8 to 30V. Simulation results demonstrate that the proposed current limit technique can guarantee the BUCK converter operating properly under any condition without damage.1