Zhang Min-xuan

Uniform Random Number Generator Using Leap Ahead LFSR Architecture

Uniform Random Number Generator (URNG) is a key element in most applications which run on FPGA based hardware accelerators. As multi-bits is required and a normal LFSR could only generate one bit per cycle, more than one LFSR is needed in a URNG. In this paper, we introduce a new kind of URNG using Leap-Ahead LFSR Architecture which could generate an m-bits random number per cycle using only one LFSR. We analyze its architecture, present the expression of the period and point out how to choose the taps of the LFSR. Finally, a 18-bits URNG is implemented on Xilinx Vertex ¿ FPGA.. By comparison, the Leap-Ahead LFSR Architecture URNG consumes less than 40 slices which is only 10% of what the Multi-LFSRs architecture consumes and acquires very good Area Time performance and Throughput performance that are 2.18×10-9 slices×sec per bit and 17.87×109 bits per sec.

Dimensional Bubble Flow Control and Fully Adaptive Routing in the 2-D Mesh Network on Chip

In this paper, the novel flow control strategy called dimensional bubble flow control (DBFC) is presented. The flow control strategy of DBFC builds on virtual cut-through switching and credit-based flow control mechanism and analyzes the credit value of port and the routing information of the packets to realize the point-point flow control. In the 2-D mesh network on chip, when the flow control strategy of DBFC is accepted, the adaptive dimensional bubble routing (ADBR) algorithm designed in this paper can get the goals including deadlock-free and minimal distance even if the cyclic dependencies exist. In this paper, the detail proof is provided for these conclusions. Lastly, we adapt the source code of NOXIM that is a popular simulator of on-chip networks and realize the flow control of DBFC and ADBR algorithm in NOXIM. We test the performance of ADBR on NOXIM. The simulation performance shows our scheme is superior to the usual approach such as XY dimension-order routing, with nearly 17.5% improvement in the packets latency and throughput.

Modeling and analysis of single-event transients in charge pumps

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phase-locked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.

A radiation-hardened-by-design technique for improving single-event transient tolerance of charge pumps in PLLs

A radiation-hardened-by-design (RHBD) technique for phase-locked loops (PLLs) has been developed for single-event transient (SET) mitigation. By presenting a novel SET-resistant complementary current limiter (CCL) and implementing it between the charge pump (CP) and the loop filter (LPF), the PLLs single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 93.1 % and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.

Adaptive Bubble Scheme with Minimal Buffers in Torus Networks

Bubble flow control is an efficient technique to avoid deadlock for torus networks. Critical bubble scheme can avoid intra-dimension deadlock with just one packet buffer, but has a risk of blocking. In this paper, we present a false packet protocol, design a non-blocking moveable bubble scheme for an adaptive virtual cut-through router, and the result is a fully adaptive router with minimal two virtual channels, one packet buffer per virtual channel. We compare the performance of various bubble-based schemes with simulation. Network simulation results show that moveable bubble scheme outperform traditional bubble scheme, whereas adaptive scheme performs apparently better than the other methods, avoids blocking, reduces latency, displays a throughput improvement of more than 20%, maximally up to 100%, and achieves lower latency.

A fault tolerant adaptive routing algorithm in 2D mesh network on chip

Interconnection plays a crucial role in the design of multi-core systems-on-chip (SoCs). Network on chip (NoC) has been proposed as a promising solution to simplify and optimize SoC design. In this paper, a flow control strategy called dimensional bubble flow control (DBFC) is presented for network on chip. The policy is based on virtual cut-through switching, uses credit-based flow control mechanism. Based on the flow control policy, a fault tolerant adaptive routing algorithm is designed with the benefits of deadlock-free and minimal distance. Detailed proof is provided for these conclusions. The result shows that the algorithm owns preferable performance.

Fully memory based address translation in user-level network interface

User-level communications greatly alleviate the software overhead of the communication subsystem by allowing applications to access the network interface directly. Such a direct data path requires the network interface to know the physical memory location of the buffer. Thus, efficient virtual-to-physical address translation is critical. This paper presents a efficient address translation scheme based on address-translation-table where every translation is done on the network interface controller without operating system involvement and miss handling, and zero copy data transfer can be implemented between processes. Adopting this mechanism, we design our communication subsystem oriented to cluster systems based on PCI-Express 2.0. The experimental results show the lowest one-way latency of 2.37us and the peak bandwidth of 6038MB/s, which is the fastest network interface at present.

A low-noise PLL design achieved by optimizing the loop bandwidth

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

A single-event transient hardened phase-locked loop in 0.18 µm CMOS process

By implementing a novel complementary current limiter (CCL), a phase-locked loop (PLL) has been developed for improved single-event transient (SET) tolerance in 0.18 µm CMOS process. Simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 92.8%, and reduce the recovery time of the PLL by up to 76.4% in the presence of SETs in the charge pump (CP). And it can also improve the error pulses and phase displacement of the output clock greatly. Moreover, the CCL circuit can be readily applied to other PLL topologies1.

Verilog-A based implementation for coupled model of single event transients in look-up table technique

A Verilog-A based implementation of voltage coupled model is developed for Single-Event Transients (SETs) in microelectronic circuits. By implementing a look-up table in Verilog-A, the SET current source performs well and consents with the results from Technology CAD (TCAD) based mix-mode simulation. Simulation results from Synopsys Hspice 2008 indicates that the method proposed in this paper correctly reveals the current “tail” which reflects the equilibrium course of charge collection. Moreover, the Verilog-A based method speeds up the simulation by over 18,000 times than the mix-mode simulation and is also faster than the piecewise linear source (PWL). Furthermore, this Verilog-A based LUT method cooperates with the design flow well and can be easily applied to various applications with wide supports of industrial EDA tools1.