Li Shaoqing

Modeling and analysis of single-event transients in charge pumps

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phase-locked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.

Verilog-A based implementation for coupled model of single event transients in look-up table technique

A Verilog-A based implementation of voltage coupled model is developed for Single-Event Transients (SETs) in microelectronic circuits. By implementing a look-up table in Verilog-A, the SET current source performs well and consents with the results from Technology CAD (TCAD) based mix-mode simulation. Simulation results from Synopsys Hspice 2008 indicates that the method proposed in this paper correctly reveals the current “tail” which reflects the equilibrium course of charge collection. Moreover, the Verilog-A based method speeds up the simulation by over 18,000 times than the mix-mode simulation and is also faster than the piecewise linear source (PWL). Furthermore, this Verilog-A based LUT method cooperates with the design flow well and can be easily applied to various applications with wide supports of industrial EDA tools1.

Static timing analysis in Dual-Rail Precharge logic based DPA resistant circuit design

Dual-Rail Precharge (DRP) logic is an efficient countermeasure against Differential Power Analysis (DPA) attack. The existing DRP logic based design method starts from a standard design flow supported by commercial EDA tools. Virtual single ended gates, instead of real DRP logic gates, are used during synthesis, placement and routing. As a result, static timing analysis becomes a problem at these design phases. In this paper, we discuss the transition behavior of DRP logic, and present a method to build the delay models of virtual single ended gates. By using these delay models, the static timing analysis for the virtual single ended circuit can represents the actual signal propagating delay in DRP logic circuit. Hence the EDA tools can do timing optimization with accurate delay information. Experimental results on a DRP logic based AES cryptographic coprocessor show the effectiveness of the proposed method.