Zhaoyun Tang

Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22 nm node pMOSFETs

Pattern dependency of selective epitaxy of Si1 xGex (0.20 6 x 6 0.45) grown in recessed source/drain regions of 22 nm pMOSFETs has been studied. A complete substrate mapping over 200 mm wafers was performed and the transistors’ characteristics were measured. The designed SiGe profile included a layer with Ge content of 40% at the bottom of recess (40 nm) and capped with 20% Ge as a sacrificial layer (20 nm) for silicide formation. The induced strain in the channel was simulated before and after silicidation. The variation of strain was localized and its effect on the transistors’ performance was determined. The chips had a variety of SiGe profile depending on their distance (closest, intermediate and central) from the edge of the 200 mm wafer. SiGe layers with poor epi-quality were observed when the coverage of exposed Si of the chip was below 1%. This causes high Ge contents with layer thicknesses above the

Physical understanding of different drain-induced-barrier-lowering variations in high-k/metal gate n-channel metal-oxide-semiconductor-field-effect-transistors induced by charge trapping under normal and reverse channel hot carrier stresses

In this paper, the drain induced barrier lowering (DIBL) variations in High-k/Metal gate n-channel metal–oxide–semiconductor field effect transistor under the normal and reverse channel hot carrier (CHC) stress are studied. It is found that DIBL decreases under normal CHC stress mode while increases under reverse CHC mode. The different DIBL variation under normal and reverse CHC stresses is proposed to be attributed to stress-induced charge trapping by cold carriers from the channel rather than hot carriers from the pinch off region, which can be explained by energy band bending theory.

Block Adjustment of a Group of Overlapping CCD Images

Since the field of view of a CCD is usually too small to cover enough reference stars, the block adjustment (BA) of CCD overlapping images is proposed in order to extend the sky coverage of observations, mitigate the effect of the position biases of reference stars, and consequently improve the local reference frame (LRF) of the observation. Observational equations of BA are given in vectorial expressions for the sake of easy understanding and programming. Investigation of the extrapolation of linear and nonlinear models illustrates that the nonlinear terms in CCD models should be determined and eliminated before implementing BA. The BA method is tested by simulated data as well as CCD observations, which shows that the application of BA to the overlapping observations could effectively improve the LRF of the observation and provide homogeneous results.

Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process

Positive bias temperature instability (PBTI) characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 eV, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.

Impacts of Back Gate Bias Stressing on Device Characteristics for Extremely Thin SoI (ETSoI) MOSFETs

In this letter, investigations of impacts of back bias stressing on extremely thin SoI MOSFETs with channel thickness varying from 11 to 4 nm are presented. For a given gate length (LG), with back bias stressing from -20 to 20 V, drain-induced barrier lowering (DIBL) with small values are obtained due to increment of carrier confinement toward the top gate for pMOSFET. While with enlargement of back bias voltage stressing from -40 to 40 V, the DIBL behaviors are different for channel thickness from 11 to 4 nm. The DIBL with channel thickness of 4 nm is consistent down to small value along with positive gate bias stressing. While for channel thickness of 7 and 11 nm, the DIBL both changes to large values at two ends of voltage stressing. In addition, subthreshold swing gets worse with more positive back gate bias (BGB) stressing. In addition, smaller channel thickness would lead to even more degraded subthreshold swing and poor gate controllability by applying a large BGB stressing. These are mainly due to high electric field in the channel induced by BGB. High positive BGB would lead to an enlargement of depletion width at the channel corner and short channel effect would get worse. In addition, high electric field is bad for channel mobility, which leads to degraded subthreshold swing.

Impact of TaN as Wet Etch Stop Layer on Device Characteristics for Dual-Metal HKMG Last Integration CMOSFETs

TaN as wet etch stop layer is implemented in dual-metal high- k/metal gate last integration CMOSFETs. Impacts of TaN on device characteristics are investigated. With thicker TaN, flat-band voltages (Vfb) of both n- and p-FETs shift to zero value position. Sensitivities of TaN thickness on Vfb are obtained with 81 and -114 mV/nm for n- and p-FETs, respectively. It could be served as an important enhancement tuning factor for threshold voltage (Vth) adjustment in CMOSFETs due to contributions of TaN on Vth values are in the same direction. With CMOS technology moving to below 22-nm node, it is crucial to control amount of wet etch of TaN layer, otherwise device characteristics would be impacted and double hump happens.

Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs

This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for the p-channel metal-oxide-semiconductor field-effect transistors fabricated the by gate-last process. It is found that work function (WF) of multilayer ALD titanium nitride/physical vapor deposition titanium/chemical vapor deposition titanium nitride (ALD TiN/PVD Ti/CVD TiN) MG in devices of short channels is larger than in devices of long channels. This mainly results from different ALD TiN crystal orientations for devices with different gate lengths, that is, TiN(100) for devices with short gate length, whereas TiN(111) for devices with long gate length. The WF of ALD TiN(100) is larger than TiN(111). Meanwhile, because of the property of PVD sputtering, the Ti layer is thinner in devices of short channels than in devices of long channels. Our results on MOSCAP show that the flat-band voltage (Vfb) for TiN MG with a Ti layer is reduced by 0.2 V. Taking all the aforementioned into account, Vth roll-up is suppressed as the gate length shrinks, leading to the mitigation of RSCE.

Impact of critical geometry dimension on channel boosting potential in 3D NAND memory

The impact of polysilicon thickness (THK-poly) and channel hole diameter (CHCD) on channel boosting potential during program inhibit has been studied with Sentaurus device simulator for three dimensional (3D) NAND memory. According to the distribution of boosting potential along the channel, the potential level of thinner THK-poly is higher than that of thicker one. Moreover, the correlation between boosting potential and CHCD also depends on the THK-poly. In the case of 20nm THK-poly, strong dependence between potential and CHCD is observed. When the THK-poly decreases to 5nm, boosting potential is almost independent with the CHCD. Our results provide guidance for predicting and optimizing the program disturbance characteristic for highly reliable 3D NAND flash memory.

String select transistor leakage suppression by threshold voltage modulation in 3D NAND Flash Memory

Single drain select transistor (DSL) in 3D Flash memory may exhibit higher leakage as compared with DSL in 2D NAND, because of worse subthreshold swing characteristics due to poly-Si channel. Select transistor leakage suppression is essential in 3D NAND Flash Memory, in consideration of boosting potential and program disturbance. Compared to single Si drain select transistor in 2D planner Flash Memory, a novel dual cylindrical thin film transistor is proposed as drain select device to suppress leakage for good boosting performance in 3D NAND flash. And a novel measurement approach is also proposed to quantify leakage of drain select transistor in program inhibit case. The effect of Vth modulation on leakage is evaluated with this new DSL approach in this work. Single poly-Si cylindrical transistors demonstrated to be not applicable in 3D NAND because of high leakage. And the optimized Vth modulation pattern of dual transistors, with lower T1 Vth and higher T2 Vth has been found for good leakage suppression, which is beneficial for self-boosting performance of 3D NAND cell string.

Simulation on threshold voltage of L-shaped bottom select transistor in 3D NAND flash memory

A comprehensive simulation analysis method is proposed to improve the bottom select gate (BSG) transistors Vth distribution by adopting under-channel implant in this work.