Zheng Song

A Fully Integrated 60-GHz 5-Gb/s QPSK Transceiver With T/R Switch in 65-nm CMOS

A fully integrated 60-GHz 5-Gb/s quadrature phase-shift keying (QPSK) transceiver with the transmit/receive (T/R) switch in 65-nm CMOS is presented. By utilizing the co-design of the T/R switch with the power amplifier (PA)/low-noise amplifier, π-type wideband passive network technique, as well as the modified distributed-amplifier-based PA, the RF bandwidth of the transmitter (TX)/receiver (RX) is extended to 5 GHz. An inductorless wideband programmable gain amplifier with negative capacitive neutralization, consisting of two modified Cherry-Hooper amplifier stages, provides 18-dB variable gain range with enough bandwidth. Due to the proposed bandwidth extension techniques, the measured double-side link bandwidth of the TX/RX is wider than 5 GHz so that 5-Gb/s QPSK communication could be supported. A direct QPSK modulator and mixed-signal QPSK demodulator are integrated to avoid the high-power high-complexity analog-digital converter/digital-analog converter and high-speed digital baseband processing. Together with the integrated T/R switch, the power consumption and the cost of the transceiver are significantly lowered while achieving up to 5-Gb/s data rate. The local oscillating signals and various clocks are provided by a fully differential phase-locked loop frequency synthesizer with -97.2-dBc/Hz phase noise at 1-MHz offset from a 40-GHz carrier. The measured error vector magnitude of the TX is -21.9 dB, while the bit error rate of the RX with a -52-dBm sine-wave input is below 8e-7 when transmitting/receiving 5-Gb/s data. The transceiver is powered by 1.0- and 1.2-V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer, which are powered by a 2.5-V supply) and consumes 135 mW in the TX mode and 176 mW in the RX mode, with a chip area of 3 mm × 2 mm.

A 2.7-mW 1.36–1.86-GHz LC-VCO With a FOM of 202 dBc/Hz Enabled by a 26%-Size-Reduced Nano-Particle-Magnetic-Enhanced Inductor

This paper reports the first LC voltage-controlled oscillator (LC-VCO) in CMOS utilizing a novel nontraditional compact inductor with integrated vertical nano particles magnetic core (Ni-Zn-Cu) to improve the figure-of-merit (FOM) of the VCO circuit. The new magnetic-enhanced inductor, fabricated in an integrated-circuit back-end using a CMOS-compatible process, improves inductance density ( L-density) and quality factor ( Q-factor) up to 7 GHz. A 1.36-1.86-GHz VCO with a nano-ferrite-integrated inductor was fabricated in a 180-nm RF CMOS. Measurements show that the magnetic-cored inductor improves the L-density and Q-factor by 49.8% and 59.2% at 1.8 GHz, respectively, while reducing the size by 26%. The VCO achieves reduced power consumption of 2.7 mW at a 1.8-V supply, low phase noise of less than -121, and -126 dBc/Hz at 100-kHz and 1-MHz frequencies offset, and a high FOM of 202 dBc/Hz. This prototype VCO demonstrates that the new vertical-nano-magnetic-cored inductor technology is a potential solution to high-performance low-cost compact RF systems-on-chip.

A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications

A fully-integrated wireless transceiver (TRX) is presented for 750~960MHz narrowband IoT applications by utilizing the guard band of mobile communication systems. The TRX consists of a low-IF receiver with 180 kHz signal bandwidth, a mixed-signal polar transmitter with 3.75 kHz signal bandwidth and a fractional-N frequency synthesizer. Current passive mixer is employed in the low-IF receiver to achieve lower 1/f noise and higher linearity. The on-chip I/Q imbalance calibration is integrated to improve the image rejection ratio (IRR) which could be realized automatically cooperated with one FPGA. The transmitter features polar architecture and inverse class-D PA to achieve high output power and efficiency. The thermometer coding and binary-coding-based array placement simplify the DPA layout and reduce the mismatch between the DPA cells. The RX achieves 4.01dB NF, 48dB IRR and 5~65dB dynamic range. The DPA provides 23.2dBm maximum saturation power with 44.5% PAE. Furthermore, TX system verifications demonstrate 3.87% EVM for 891MHz n/4-DQPSK signals at 18.87dBm output power with -40dBc out-of-band rejection. The transmitter achieves a dynamic range from -35dBm to 20dBm while the demodulation threshold of the system is 10% (EVM).

A multi-mode complex bandpass filter with gm-assisted power optimization and I/Q calibration

This paper presents a 65nm multi-mode complex band-pass filter (C-BPF) used in low-IF GNSS receivers. It supports the bandwidth of 4MHz, 10MHz and 18MHz, and can be centered at 4.2MHz, 6.1MHz, 12.3MHz and 28MHz. The OTAs served in the filter are realized in arrays which makes the power consumption scalable among different operation modes. In addition, assistant transconductors (assistant-gm) are adopted to compensate the outputs of each OTA stage, which in turn saves at maximum 9mA DC current for the whole filter. In order to achieve higher than 30dB image rejection ratio (IRR), another group of assistant-gms are introduced to the input stage for I/Q mismatch calibration, which is able to regulate a maximum ±3dB amplitude imbalance and ±5° phase imbalance. The filter consumes less than 10mA in the 28MHz-IF, 18MHz-bandwidth mode, and achieves >31dB IRR with the maximum I/Q amplitude and phase mismatch.

A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signal bandwidth, and a fractional-N frequency synthesizer. Passive current mixer is employed in the receiver to improve the linearity and avoid the sensitivity degradation due to 1/

A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver

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A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers

noise. Automatic I/Q imbalance calibration is integrated to improve image rejection ratio (IRR) with the aid of external FPGA. The transmitter is implemented in the digital polar architecture to improve the narrow-band spectrum purity, integrated with an inverse Class-D digital power amplifier (DPA) to achieve high output power and efficiency. A Class-C voltage-controlled oscillator with automatic frequency control assisted the dynamic gate biasing technique is used in the fractional-N PLL frequency synthesizer. Two prototypes are implemented in 180-nm CMOS. By optimizing analog baseband configuration in the receiver and utilizing the revised thermometer-coding and binary-coding-based array placement in the DPA, the receiver achieves 4.0-dB noise figure, 48-dB IRR, and 60-dB PGA dynamic range, and the DPA outputs 23.2dBm maximum saturation power with 44.5% PAE. Furthermore, the transmitter system verifications demonstrate 3.87% error-vector magnitude (EVM) for 891 MHz

A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations

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A multi-mode blocker-tolerant GNSS receiver with CT sigma-delta ADC in 65nm CMOS

/4-DQPSK signals at 18.87-dBm output power with −40-dBc out-of-band rejection. The transmitter achieves a dynamic range from −35 to 20 dBm when the demodulation EVM threshold of the system is set to 10%.

A fully integrated reconfigurable low-power Sub-GHz transceiver for 802.11ah in 65nm CMOS

A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm2 die area and consumes 1.82mA (I and Q path) from a 1.7V supply.