Haikun Jia

A 47.6–71.0-GHz 65-nm CMOS VCO Based on Magnetically Coupled

A wide tuning range millimeter-wave voltage-controlled oscillator (VCO) based on a magnetically coupled π-type LC network in 65-nm CMOS is proposed. By configuring the switched negative-resistance unit, the VCO can oscillate at the even mode or the odd mode of the magnetically coupled π-type LC network, thus the tuning range is widened without introducing the switch loss into the resonator. The proposed VCO achieves a measured continuous tuning range of 39%, from 47.6 to 71.0 GHz. The measured phase noise for a 47.6-GHz carrier at the even mode and 56.2-GHz carrier at the odd mode are -110.3 and -107.3 dBc/Hz at 10-MHz offset with a corresponding FOMT of -185.5 and -183.9 dBc/Hz, respectively. The measured phase noise in the whole frequency tuning range varies from -101.7 to -113.4 dBc/Hz at 10-MHz offset, while the corresponding figure-of-merit (FOM) and FOMT vary from -167.8 to -179.0 dB and -179.6 to 190.6 dB, respectively. The VCO core consumes 8.9-10.4-mA current from 1.0-V power supply and 320 × 230 μm 2 die area.

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A 60-GHz dual-mode power amplifier (PA) with efficiency enhancement at low output power in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver stages and one transformer-based output stage. The dual-mode output stage is reconfigured into a stacked-transistor amplifier with a 2.5-V power supply in high-power (HP) mode for high-power-handling capability and a cascode amplifier with a 1.2-V power supply in low-power (LP) mode for efficiency enhancement at low output power. The measured results show that the presented PA achieves a small-signal gain of 23.5/21.3 dB, a saturated output power value of 17.6/11.4 dBm, a 1-dB output power value of 12.5/4.7 dBm, and a peak power-added-efficiency (PAE) value of 20.4%/13.3% in the HP/LP mode at 60 GHz, respectively. The PAE at 10-dBm output power is improved by 2.8x (10.6% versus 3.8%) by utilizing the LP mode compared with the HP-mode-only PA. The total chip area is 0.68 mm × 0.35 mm, including pads.

-Type LC Network

A miniaturized Marchand balun combiner is proposed for a W-band power amplifier (PA). The proposed combiner reduces the electrical length of the transmission lines (transmission line) from about 80 ^° to 30 ^°, when compared with a conventional Marchand balun combiner. Implemented in a 1-V 65-nm CMOS process, the presented PA achieves a measured saturated output power of 11.9 dBm and a peak power-added efficiency of 9.0% at 87 GHz. The total chip area (with pads) is 0.77×0.48 mm², where the size of the balun combiner is only 0.36×0.13 mm².

A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power

A fully integrated 60-GHz 5-Gb/s quadrature phase-shift keying (QPSK) transceiver with the transmit/receive (T/R) switch in 65-nm CMOS is presented. By utilizing the co-design of the T/R switch with the power amplifier (PA)/low-noise amplifier, π-type wideband passive network technique, as well as the modified distributed-amplifier-based PA, the RF bandwidth of the transmitter (TX)/receiver (RX) is extended to 5 GHz. An inductorless wideband programmable gain amplifier with negative capacitive neutralization, consisting of two modified Cherry-Hooper amplifier stages, provides 18-dB variable gain range with enough bandwidth. Due to the proposed bandwidth extension techniques, the measured double-side link bandwidth of the TX/RX is wider than 5 GHz so that 5-Gb/s QPSK communication could be supported. A direct QPSK modulator and mixed-signal QPSK demodulator are integrated to avoid the high-power high-complexity analog-digital converter/digital-analog converter and high-speed digital baseband processing. Together with the integrated T/R switch, the power consumption and the cost of the transceiver are significantly lowered while achieving up to 5-Gb/s data rate. The local oscillating signals and various clocks are provided by a fully differential phase-locked loop frequency synthesizer with -97.2-dBc/Hz phase noise at 1-MHz offset from a 40-GHz carrier. The measured error vector magnitude of the TX is -21.9 dB, while the bit error rate of the RX with a -52-dBm sine-wave input is below 8e-7 when transmitting/receiving 5-Gb/s data. The transceiver is powered by 1.0- and 1.2-V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer, which are powered by a 2.5-V supply) and consumes 135 mW in the TX mode and 176 mW in the RX mode, with a chip area of 3 mm × 2 mm.

A W-Band Power Amplifier Utilizing a Miniaturized Marchand Balun Combiner

A fully-integrated 77 GHz frequency doubling two-path phased-array frequency-modulated continuous-wave (FMCW) transceiver for automotive radar applications is proposed. By utilizing the frequency doubling scheme, the chirp bandwidth is improved, and the complexity of the frequency synthesizer and the insertion loss of the local-oscillating (LO) distribution network are both reduced. Top-injected coupled resonator based wide locking range technique is proposed in the frequency doublers to minimize the required injection power to cover the chirp bandwidth plus enough PVT variation margin, and therefore reduce the power consumption of the LO distribution network. Current-reused coupled resonator technique is utilized to implement the LO phase shifting in each receiving path. The digitally controlled artificial dielectric-based transmission lines are inserted in the low noise amplifiers to provide the operation frequency calibration capability. The receiving two-path signals are converted into intermediate frequency by low flicker noise current-mode passive mixers and then combined in the trans-impedance amplifier, followed by the reconfigurable analog baseband processing. Fabricated in 65 nm CMOS, the FMCW transceiver has achieved 1.93 GHz maximum chirp bandwidth, 12.9 ~ 13.2 dBm maximum transmitting power, and 47.8 ~ 100.7 dB programmable receiving conversion gain. The transceiver consumes 343 mW power and 4.64 mm2 chip area including all of the pads.

A Fully Integrated 60-GHz 5-Gb/s QPSK Transceiver With T/R Switch in 65-nm CMOS

Co-design of 60-GHz wideband front-end integrated circuit (IC) with on-chip transmit/receive (T/R) switch in 65-nm CMOS is presented. Passive macro-modeling (pmm) is utilized to convert S-parameter files from passive component electromagnetic simulations to state-space models in circuit netlist format that could be used in a commercial SPICE simulator for various analyses without convergence issues. The co-design of the on-chip switch and the low-noise amplifier (LNA)/power amplifier could achieve wideband matching and reduce the effects of insertion loss of the on-chip T/R switch. Combining with the gain-boosting technique in the LNA design and lumped-component-based design methodology, the implemented 60-GHz front-end IC with an on-chip T/R switch achieves 3-dB gain bandwidth (BW) of 12 GHz with a maximum gain of 17.8 dB and minimum noise figure of 5.6 dB in the receiver mode and 3-dB gain BW of 10 GHz with saturated output power of 5.6 dBm in the transmitter mode, and only consumes 1.0 mm × 1.2 mm die area (including pads).

A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar

A W-band injection-locked frequency doubler in 65-nm CMOS is proposed. By using the coupled resonator, a 69.2-94.6-GHz locking range has been achieved with a 3.4- ~ 4.1-dBm injected power. The second-order harmonic current is injected from the top of the resonator, which avoids the source degeneration issue. The measured phase-noise deterioration from that of the injected signal at 100-kHz offset is only 6.2 dB, which is close to the theoretical calculation. The doubler occupies a die area of 0.16 mm2, including the buffers, and draws 9.7- ~ 11.4-mA current from a 1.0-V power supply excluding the buffers.

Co-Design of 60-GHz Wideband Front-End IC With On-Chip T/R Switch Based on Passive Macro-Modeling

To support 16-QAM modulation in E-band applications, phase-locked loops (PLLs) are required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of -90dBc/Hz @1MHz [1], which are still very challenging even with aggressive CMOS scaling [2]. Another issue associated with PLLs is the difficulty to integrate on-chip loop filters. Active loop filters are employed to scale down the loop filter capacitors and enable them to be fully integrated on-chip [3]. However, this method suffers from large active noise induced by the op-amp. Moreover, as the capacitance is reduced, the resistor value has to be increased to maintain the same zero frequency, leading to higher thermal noise and limiting achievable scaling factor. Another method is to integrate digital loop filters in all-digital PLLs (ADPLLs) [4]. Unfortunately, the quantization noise of digitally-controlled oscillators (DCOs) becomes a bottleneck to achieve good phase noise due to their limited frequency resolution. Furthermore, E-band DCO oscillation frequency is more sensitive to capacitor variation, making it even more difficult to achieve high frequency resolution. To address these issues, this paper proposes a 70.5-to-85.5GHz PLL with an injection-locked frequency tripler (ILFM3) and passive scaling to increase the effective capacitor for the loop filter by 100 times.

A W-Band Injection-Locked Frequency Doubler Based on Top-Injected Coupled Resonator

A 38- to 40-GHz current-reused active phase shifter based on a coupled resonator is proposed. The coupled resonator is used to increase the phase-shifting range and reduce the gain variation along with the phase-shifting value. The digital controlled artificial dielectric transmission lines are used instead of varactors to achieve high quality and directly digital control, and a current reuse technique is employed to reduce the power consumption. Implemented in 65-nm CMOS, the phase shifter occupies a chip area of 0.16 mm2 without pads and consumes a 6.6 mA current from a 1.0 V power supply. Measured results show that the gain variation of the phase shifter is less than 1 dB over 38-40 GHz while achieving the 90 ° phase-shifting range.

25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter

A simple and robust self-healing technique for millimetre-wave (mm-wave) amplifiers is proposed. The self-healing technique can correct the operation frequency shifting of the amplifier (including its input and output impedance matching shifting) due to process, voltage, and temperature variations and modelling inaccuracy. A mm-wave amplifier with digitally controlled artificial dielectric transmission lines as fine frequency tuning components and an on-chip power detector as the frequency shifting detector has been implemented in 65 nm complementary metal–oxide–semiconductor to verify the effectiveness of the technique. The operating frequency of five amplifier chips is calibrated by running the self-healing algorithm on a field-programmable gate array development board. On average, the gain of the amplifier is improved by 2.60 dB from 13.66 to 16.26 dB and the input matching is improved by 12.78 dB from −4.89 to −17.67 dB at 56 GHz after the proposed self-healing procedure.