Zhigang Hao

Performance bound analysis of analog circuits considering process variations

In this paper, we propose a new time-domain performance bound analysis method for analog circuits considering process variations. The proposed method, called TIDBA, consists of several steps to compute the bound performances in time domain. First the performance bound in frequency domain is computed for a linearized analog circuits by an variational symbolic analysis method and the Kharitonovs functions. Then the time domain performance bound is computed via a new general-signal transient bound analysis method. The new algorithm can give transient lower bound and upper bound of the performance variations affected analog circuits accurately and reliably. Experimental results from two industry benchmark circuits show that TIDBA gives the correct bounds for the Monte Carlo analysis while it delivers one order of magnitude speedup over the Monte Carlo method.

Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks

The shrinking technology feature size and dense large-scale integration make process variation a challenging issue directly confronting the latest design automation tools. Process variation causes severe variation in interconnect networks, including very large-scale integrated interconnect structures, such as clock trees, clock mesh, power-ground networks, and other wiring structures in 3-D integrated circuits. The traditional moment computation techniques are only partly useful for analyzing such variational problems, however, their computational efficiency cannot meet the quickly rising needs, such as statistical analysis. This paper presents a novel symbolic moment calculator (SMC) for variational interconnect analysis. The moment calculator is constructed in a regular data structure that incorporates binary decision diagrams for data storage and computation. Given an interconnect circuit, such a computation diagram has to be constructed only once and can be repeatedly invoked for computation of moments with varying parameter values. Also, the SMC is friendly to interconnect synthesis in that it can be incrementally modified according to the modifications made to the circuit structure. Applications of the SMC for fast moment computation, sensitivity analysis, and statistical timing analysis are addressed. Significant efficiency is demonstrated comparing to other existing methods.

Statistical full-chip dynamic power estimation considering spatial correlations

Estimating the dynamic powers is crucial for power and energy efficient chip designs. With increasing variability from manufacture processes, dynamic powers can manifest significant variations due to uncertainties in device geometry and delay variations. In this paper, we propose a new statistical dynamic power estimation method considering the spatial correlation in process variation. We first show that channel length variation have significant impacts on the dynamic power of a gate. To consider the spatial correlation of channel length variation, we adopt a newly proposed spatial correlation model where a new set of uncorrelated variables are defined over virtual grids to represent the original physical random variables by least-square fitting. To compute the statistical dynamic power of a gate on the new set of variables, the new method applies the orthogonal polynomials based method. We use the segment-based statistical power method to consider impacts of the glitch variations on dynamic powers. The orthogonal polynomial of a statistical gate power is computed based on switching segment probabilities. The total full chip dynamic power expressions are then computed by summing up resulting orthogonal polynomials (their coefficients). Experimental results show that the proposed method has about 53X speedup over recently proposed statistical dynamic power analysis method and many orders of magnitudes over the Monte Carlo method.

An efficient statistical chip-level total power estimation method considering process variations with spatial correlation

In this paper, we proposed an efficient statistical chip-level total power estimation method considering process variations with spatial correlation. Instead of computing dynamic power and leakage power separately, the new method compute the total power via circuit level simulation under realistic input testing vectors. To consider the process variations with spatial correlation, we first apply principle factor analysis method (PFA) to transform the correlated variables into uncorrelated ones and meanwhile reduce the number of resulting random variables. Afterwards, Hermite polynomials and sparse grid techniques are used to estimate total power distribution in a sampling way. The proposed method has no restrictions on models of statistical distributions for total powers. The proposed method works well when strong spatial correlation exists among random variables in the chip. Experimental results show that the proposed method has 78X times speedup than the Monte Carlo method under fixed input vector and 26X times speedup than the Monte Carlo method considering both random input vectors and process variations with spatial correlation.

A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources

Mesh circuits typically consist of many resistive links and many sources. Accurate analysis of massive mesh networks is demanding in the current integrated circuit design practice, yet their computation confronts numerous challenges. When variation is considered, mesh analysis becomes a much harder task. This paper proposes a symbolic computation technique that can be applied to the moment-based analysis of mesh networks with multiple sources. The variation issues are easily taken care of by a structured computation mechanism, which can naturally facilitate sensitivity based analysis. Applications are addressed by applying the computation technique to a set of mesh circuits with varying sizes.

Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees

Capacitive and inductive coupling issues are hard to analyze in general; however, they are critical for signal integrity (SI) analysis in the contemporary integrated circuit technology. This paper presents a sensitivity based computation approach to coupled RLC trees for statistical signal integrity analysis. This technique is intended for use in SI-driven placement and routing.

Statistical full-chip total power estimation considering spatially correlated process variations

In this paper, we propose an efficient statistical full-chip total power estimation method considering process variations with spatial correlation. Traditionally, dynamic power and leakage power were computed separately as leakage power is more susceptible to process variations. But in the end, it is total power that designers will be concerned with. We propose a new method to compute the statistical total power via circuit level simulation under realistic input testing vectors. To consider the process variations with spatial correlation, we first apply principle factor analysis method (PFA) or its weighted version (wPFA) to transform the correlated variables into uncorrelated ones and meanwhile reduce the number of resulting random variables. Afterwards, Hermite orthogonal polynomials and sparse grid techniques are used to estimate total power distribution in a sampling way. The proposed method has no restrictions on models of statistical distributions for total powers. The method works well when strong spatial correlation exists among random variables in the chip. Experimental results show that the proposed method has 100X times speedup than the Monte Carlo method under fixed input vector and 20X times speedup than the Monte Carlo method considering both random input vectors and process variations with spatial correlation.

New approaches to interconnect macromodeling with explicit delay extraction

IC design automation relies on macromodels for interconnect analysis. For simulation speed, low-order macromodels are in general preferred. Besides rational macromodels, explicit delay components e-taus are of special interest in interconnect timing. This paper investigates new approaches to modeling interconnects in the form of multiplying a rational function by a delay component. Fitting-based techniques are used both in the time-domain and in the frequency-domain for the purpose of hybrid modeling using sampled data. A technique for passivity test is also introduced. Examples are given to demonstrate the effectiveness of the proposed methodology.

Battery state of charge estimation using adaptive subspace identification method

Estimation of battery state of charge (SOC) is essential for many emerging battery powered applications such as smart phones, electric and hybrid electric vehicles. In this paper, we propose a new battery SOC estimation method using adaptive subspace identification method. The subspace identification method is a numerically robust approach and is used to build the dynamic linear model based on batterys terminal voltages and current. To deal with the nonlinearity of the battery, the transient battery terminal voltages and current are partitioned into piecewise linear regions and subspace identification is performed on each linear region. As a result, the battery SOC can be accurately calculated for each region. Our experiments show that the new method has an error margin of 1.4% from ideal SOC values as given by Dualfoil, a powerful battery simulator. This outperforms the least square estimation algorithm, which is found to have a higher error margin of 4.5% for some load profiles, while not converging at all for some other load profiles.

Parametric analysis of multiple interconnects via canonical reduced order modeling

For design nodes at 65 nm and below, timing will essentially be a statistical measure of the fabricated circuit and heavily correlated with process variation. This paper proposes a novel parametric interconnect analysis using canonical reduced order modeling. Models in canonical forms have the feature of a small number of free model parameters. This property can be made use of effectively for parametric analysis via interpolation. Experimental results demonstrate the effectiveness of the proposed methodology.