Zhihui Xiong

A platform-based SoC hardware/software co-design environment

This work presents a platform-based SoC hardware/software co-design environment named HSCDE. It introduces the overall structure of HSCDE, describes the platform-based SoC system modeling technology, and algorithm based hardware/software partitioning technology and hierarchical directed acyclic graph based performance constraint assignment technology. HSCDE supports platform-based SoC hardware/software co-design methodology. It supports almost all the design phases from SoC system modeling to RTL level SoC system. It divides SoC hardware/software co-design into system modeling level (level 1), virtual components level (level 2) and real components level (level 3), and it performs the 2 mappings among the 3 design levels by design planning (mapping 1) and virtual-real synthesis (mapping 2). We have done SoC system design for MP3 player SoC, MEPG2 player SoC and CDMA wireless communication SoC in HSCDE environment. Results show that HSCDE effectively supports platform-based SoC hardware/software co-design methodology; it enhanced system reuse of existing SoC design. Statistics indicate an average of 10%/spl sim/25% revisions on platform templates for a new SoC design, and we achieved platform template reuse ratio by 75%/spl sim/90%.

Fast Panorama Unrolling of Catadioptric Omni-Directional Images for Cooperative Robot Vision System

For omni-directional imaging based cooperative robot vision system, panorama unrolling is an important problem. We present an eight direction symmetry reuse algorithm for this problem, principles of this algorithm are: 1) Treat the original image to be unrolled as a series of co-centric circles, and uniformly partition them into eight parts of symmetrical sector regions. 2) According to symmetry principle in spatial geometry, we construct the symmetrical transform relations pixel coordinates among these regions. So, we need compute only one region of pixel coordinate for panorama unrolling, by use of complex ray-trace coordinate mapping, while the other seven parts of regions can be determined by symmetrically reusing results from the first region, which reduces seven-eighths computational burden for ray-tracing method. Experiments indicate that, under the same precision, our algorithm improves 3.28 times of unrolling speed compared with ray-trace unrolling method. In omnidirectional video with look-up table method, the idea of eight direction symmetry reuse can also be used to reduce the look-up table size to only one-eighth of the original table.

Hardware/software partitioning for platform-based design method

Ant System Algorithm has the advantages of positive feedback and efficient convergence in optimal searching, but it lacks initial pheromone, which greatly limits this algorithms searching speed. Oriented to Platform-Based Design of System-on-a-Chip, we present a hardware/software bi-partitioning algorithm based on Ant System, Algorithm with Initial Pheromone. The main ideas are: a). Reuse the partitioning result of reference design provided by Platform-Based Design method as current designs initial partitioning, which is then converted into the initial pheromone needed by Ant System Algorithm. b). Search for the optimal partitioning scheme with the Ant System Algorithm based on the initial pheromone. Our algorithm adopts system level reusing feature of Platform-Based Design method to prevent the disadvantages of Ant System Algorithm. Experiments show our algorithm improves the efficiency of Ant System Algorithm by an average of forty percent.

Hardware/software co-design using hierarchical platform-based design method

A hierarchical platform-based design (Hi-PBD) method is put forward for SoC system design. This method divides SoC system design flow into three levels (i.e. system model level, virtual components level and real components level) to achieve separation of function from structure and separation of computation from communication. Hi-PBD defines two mapping processes (i.e. design planning and virtual-real synthesis) to go through all the three design levels. Hi-PBD supports reuse of both the three level design templates and the two mapping results, which increased reusing efficiency greatly. Besides, Hi-PBD boosts up design flexibility by means of supporting revision at all the three levels, and ensures the final design target satisfies performance requirements through a novel performance constraints transmission strategy. Experiments indicate Hi-PBD method improves SoC high level design efficiency by 30%-40%, and this method achieves platform template reuse ratio by 75%-90%.

Use dynamic combination of two meta-heuristics to do bi-partitioning

In order to solve the hardware/software bi-partitioning problems in embedded system and System-on-a-Chip co-design, we put forward a novel bi-partitioning algorithm, which is based on the dynamic combination of Genetic Algorithm (GA) and Ant System Algorithm (ASA). The basic idea is: 1).Firstly, we use Genetic Algorithm to generate preliminary partitioning results, which are then converted into initial pheromone required by Ant System Algorithm, and finally we use Ant System Algorithm to search for the optimal partitioning scheme; 2).While the Genetic Algorithm is running, we determine the best combination time of GA and ASA dynamically, thus, the Genetic Algorithm avoids too early or too late termination. Experiments show that our algorithm excels GA and ASA in performance; moreover, we discover that the bigger partitioning problems are, the better our algorithm performs.

Hardware/software co-design environment for hierarchical platform-based design

To facilitate the design of SoC (System-on-a-Chip), we present a hardware/software co-design environment called HSCDE. In this paper, some critical techniques related to HSCDE are revealed, including Platform-Based SoC modeling technology and ant algorithm based hardware/software partitioning technology. HSCDE environment divides SoC hardware/software co-design processes into three design levels, and it also supports the mappings among these design levels by two design mapping processes. Experimental results show that HSCDE effectively supports hierarchical Platform-Based SoC hardware/software co-design methodology, and further statistics reveal that an average of 10%~25% revisions on platform templates are required to get a new SoC design.