Zhijian Xie

A Generalized Architecture for the Frequency- Selective Digital Predistortion Linearization Technique

This paper presents a new architecture for the frequency-selective digital predistortion (DPD) for two- and three-band power amplifier (PA) linearization. Also, largely spaced-signal DPD using a digital intermediate frequency (IF) technique is demonstrated. The algorithm used accounts for differential memory effects up to fifth order for bands that can be arbitrarily spaced. The simulation and experimental studies are performed using various signal sets; two- and three-band multitone signals with various tone spacing, band separation, and complementary cumulative distribution function. An improvement of 10 dB over third-order linearization is demonstrated in simulation for more than 20 dB of adjacent channel power ratio reduction. The test signal and the linearization algorithm were implemented on a field-programmable gate array. The linearization algorithm was applied to an RF amplifier at 700-900 MHz. For the two-band case, more than 15 dB on the in-band, 13 dB on the third, and 5 dB on the fifth intermodulation distortion (IMD) cancellation were achieved. For the three-band case, more than 12 dB of IMD cancellation was observed. For largely spaced signal DPD, more than 15 dB of IMD cancellation was achieved. In the three-band case, the linearization of intermodulation byproducts overlapping with the in-band distortion is found to be of critical importance.

Model-Based Nonlinear Embedding for Power-Amplifier Design

A fully model-based nonlinear embedding device model including low- and high-frequency dispersion effects is implemented for the Angelov device model and successfully demonstrated for load modulation power-amplifier (PA) applications. Using this nonlinear embedding device model, any desired PA mode of operation at the current source plane can be projected to the external reference planes to synthesize the required multi-harmonic source and load terminations. A 2-D identification of the intrinsic PA operation modes is performed first at the current source reference planes. For intrinsic modes defined without lossy parasitics, most of the required source impedance terminations will exhibit a substantial negative resistance after projection to the external reference planes. These terminations can then be implemented by active harmonic injection at the input. It is verified experimentally for a 15-W GaN HEMT class-AB mode that, using the second harmonic injection synthesized by the embedding device model at the input, yields an improved drain efficiency of up to 5% in agreement with the simulation. A figure-of-merit is also introduced to evaluate the efficacy of the nonlinear embedding PA design methodology in achieving the targeted intrinsic mode operation given the model accuracy.

Multi-objective optimization of rotary travelling wave oscillator (RTWO) with neuro-genetic nondominated sorting algorithm

Rotary travelling wave oscillator (RTWO) represents a transmission line based technology for multigigahertz clock generation. RTWO design is a multi-parameter-multi-objective problem with tradeoffs of performance measures, power and phase noise. In this paper, non-dominated based genetic algorithm for multi-objective optimization is used to determine the Pareto optimal front of solutions for low power and phase noise with emphasis on variation of transmission line width and spacing. Optimization is followed by sensitivity assessment wherein Monte Carlo simulations and corner analysis are performed on the Pareto points with respect to process variations. The algorithm is validated in the design of RTWO whose frequency varies between 3 to 5 GHz due to varying dimensions of coupled transmission line. The optimization is a two step process. A neural network is developed from experimental data to estimate phase noise and power with transmission line width and spacing as inputs. The neural network is then coupled with genetic algorithm for subsequent design optimization. Our results show a set of solutions for width and spacing with objective functions less sensitive to process variations.

Design of 110–152 GHz rotary traveling wave oscillators in 65 nm CMOS technology

A novel rotary traveling wave oscillator (RTWO) is proposed to be an alternative architecture to generate THz signals for long distance high speed communication. As a preliminary work, the design of 110-152 GHz RTWO as the fundamental oscillators is reported in this paper. The transmission line ring, the n-transistor-only cross-coupled inverter pair (CCIP), and the bias-T for the oscillation have been investigated. RTWO with 113 GHz oscillation frequency is designed and layout in TSMC 65 nm CMOS process.

A power-aware rotary traveling wave oscillator (RTWO) design in 0.18um CMOS

RTWO represents a transmission line based technology for clock generation providing low skew, low phase noise and multiphase signal. Compared to traditional LC oscillators, one major drawback in RTWO performance is high power consumption. To minimize power consumption, a half circuit implementation of gain stage is proposed. The concept is validated by X-band RTWOs using conventional and proposed gain stage, respectively, in 0.18um CMOS technology. The proposed circuit consumes 30mW with the phase noise of -98.2 dBc/Hz at 1MHz offset compared to 38mW with the phase noise of -87.3 dBc/Hz for the conventional circuit.

Recent trends in RFID transponders

The Radio-Frequency identification (RFID) technology is one of the fast growing technologies. This paper reviews the history of RFID transponders, RFID technology, classification of RFID tags, applications, and their operating frequencies. The comparison of on-chip and off-chip antennas for RFID transponders has been discussed. This paper also addresses the recent trends and future developments in RFID technology.

Study of amplification stage limitation of rotary traveling wave oscillators

In this work, an explanation for the frequency limiting factor through analysis and board level implementation of Rotary Traveling Wave Oscillator (RTWO) is proposed. We also established and demonstrate the relation between frequency limit and the amplification stage. To utilize RTWO for high frequency application, it was realized that, varying the ring size to achieve high frequency signals is governed by a length threshold which when exceeded contribute to signal instability and in some cases the possibility of no oscillation.

Modeling Coupled Lines in 65 nm CMOS for Millimeter-Wave Applications

An analysis of the behavior of coupled lines in the 100-200 GHz frequency range is presented. Characterization of lumped and electromagnetic elements are included as a preliminary work to predict the behavior of the line in a Rotary Traveling Wave Oscillator (RTWO) integrated circuit. Using Sonnet and Agilent ADS, the simulated behavior of a coupled transmission line implemented in 65 nanometer CMOS is presented as well as the method used for modeling the lines.

X-band energy harvester with miniaturized on-chip slot antenna implemented in 0.18-μm RF CMOS

This paper presents a novel fully integrated X-band energy harvester, with on-chip antenna, matching network, and a multi-stage RF-DC rectifier implemented in IBM 0.18-μm RF CMOS technology. We investigated different matching schemes, antennas, and rectifiers with focus on the interaction between building blocks. Among different matching topologies, the series inductive scheme demonstrated the best performance for X-band to DC energy conversion. Our measurement results show that the proposed X-band RF-DC rectifier generates a 1.23 V DC output with 304 KΩ load at 9.2 GHz with -8.0 dBm input RF power, providing a power conversion efficiency of 3.1%.

A dual band passive RFID design in 0.18µm CMOS technology

This paper presents a novel fully integrated passive X-band RFID transponder, implemented in IBM 0.18-μm RF CMOS technology. The tag was designed to keep the current dissipation in the whole system to a minimum, with special emphasis on RF-DC rectifier and the voltage sensor. Interaction between the building blocks of the RFID tag was investigated and the key design issues addressed in this paper include the design of low-power RFID building blocks. The simulation results demonstrated that the proposed low-power RFID transponder can properly operate under very low input power as well as complying with the universal RFID communication standard.