Zhiyuan Yang

Electromigration-aware placement for 3D-ICs

This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSVs EM objective function is used, providing a computationally efficient way to represent TSV EM other than the finite-element-method (FEM) based simulation. Considering TSVs EM is mutually influenced by neighboring TSVs (due to TSV EMs dependence on TSV-induced thermal mechanical stress) and strongly affected by temperature, iterative optimizations are performed to obtain the optimal TSVs distribution and a desired TSVs temperature. Finally using a compact thermal model and simulated annealing, all logic gates are placed such that the desired temperature profile is reached. Results show that compared with a conventional wirelength centered 3D placer, our design achieves 3.41x longer mean-time-to-failure (MTTF), with only 3% wirelength overhead.

Co-Placement for Pin-Fin Based Micro-Fluidically Cooled 3D ICs

3D ICs with through-silicon vias (TSVs) can achieve high performance while exacerbating the problem of heat removal. This necessitates the use of more aggressive cooling solutions such as micropin-fin based fluidic cooling. However, micropin-fin cooling comes with overheads such as non-uniform cooling capacity along the flow direction and restriction on the position of TSVs to where pins exist. 3D gate and TSV placement approaches un-aware of these drawbacks may lead to detrimental effects and even infeasible chip design. In this paper, we present a hierarchical partitioning based algorithm for co-placing gates and TSVs to co-optimize the wire-length and in-layer temperature uniformity, given the logical level netlist and layer assignment of gates. Compared to the wire-length driven gate placement followed by a TSV legalization stage, our approach can achieve up to 75% and 25% reduction of in-layer temperature variation and peak temperature, respectively, with the cost of 13% increase in wire-length.Copyright

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs

Three-dimensional integration enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. A dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPUs operating points to adjust DRAMs voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAMs resilience without sacrificing performance.

Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction

This paper presents a post-placement technique for through-silicon-via (TSV) induced thermal mechanical stress reduction. Thermal mechanical stress causes several critical failures such as material fracture (interfacial delamination and silicon substrate cracking) and TSV stress migration (SM). The von Mises stress is used as a material fracture metric. An analytical TSV SM model is used, which replaces time-consuming finite-element-method (FEM) based simulation. The von Mises stress criterion and the analytical SM model are combined to form a unified placement optimization problem to alleviate both material fracture and SM problems. Considering the TSV-induced thermal mechanical stress profile strongly depends on TSV placement and thermal profile, iterative optimizations are performed to optimize the placement of TSVs and power-dissipating gates. Results show that compared to an initial reliability-unaware 3D placement, our design achieves 2.44x longer SM mean-time-to-failure (MTTF), 23% reduction in von Mises stress, with only 3% wirelength overhead.

Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks

Microfluidic cooling is considered an effective cooling method suitable for 3-D ICs. However, TSVs are placed in pin fins and coolant flows in between pin fins, so inserting more pin fins to increase the vertical bandwidth reduces the cooling capacity. This paper codesigns 3-D CPU architectures and microfluidic heatsinks to simultaneously optimize the performance and cooling capacity of 3-D ICs with microfluidic pin-fin heatsinks. The article shows that the codesign approach achieves better performance and energy efficiency than optimizing only the cooling capacity or the vertical bandwidth.

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling

Through Silicon Via (TSV) based 3D integration technology is a promising technology to increase the performance of FPGAs by achieving shorter global wire-length and higher logic density. However, 3D FPGAs also suffer from severe thermal problems due to the increase in power density and thermal resistance. Moreover, past work has shown that leakage power can account for 40\% of the total power at current technology nodes and leakage power increases non-linearly with temperature. This intensifies the thermal problem in 3D FPGAs and more aggressive cooling methods such as micro-channel based fluidic cooling are required to fully exploit their benefits. The interaction between micro-channel heat sink design and the performance of a 3D FPGA is very complicated and a comprehensive approach is required to identify the optimal design of 3D FPGAs subject to thermo-electrical constraints. In this work, we propose an analysis framework for 3D FPGAs embedded with micro-channel-based fluidic cooling to study the impact of channel density on cooling and performance. According to our simulation results, we provide guidelines for designing 3D FPGAs embedded with micro-channel cooling and identify the optimal design for each benchmark. Compared to naive 3D FPGA designs which use fixed thermal heat sink, the optimal design identified using our framework can improve the operating frequency and energy efficiency by up to 80.3% and 124.0%.

Value-driven Synthesis for Neural Network ASICs

In order to enable low power and high performance evaluation of neural network (NN) applications, we investigate new design methodologies for synthesizing neural network ASICs (NN-ASICs). An NN-ASIC takes a trained NN and implements a chip with customized optimization. Knowing the NN topology and weights allows us to develop unique optimization schemes which are not available to regular ASICs. In this work, we investigate two types of value-driven optimized multipliers which exploit the knowledge of synaptic weights and we develop an algorithm to synthesize the multiplication of trained NNs using these special multipliers instead of general ones. The proposed method is evaluated using several Deep Neural Networks. Experimental results demonstrate that compared to traditional NNPs, our proposed NN-ASICs can achieve up to 6.5x and 55x improvement in performance and energy efficiency (i.e. inverse of Energy-Delay-Product), respectively.

Design Space Modeling and Simulation for Physically Constrained 3D CPUs

Design space exploration (DSE) is becoming increasingly complex and 3D integration compounds the problem by imposing a more complex design space. Moreover, 3D design is a new frontier of CPU design, expected to rely more heavily on statistical modeling than designer intuition. Past work has used regression modeling with random sampling of the design space. In this paper we propose a directed simulation technique where intermediate predictions more efficiently direct simulation resources. Our results show over 98% model accuracy while simulating less than 5% of the design space and reducing simulation time more than 4.5x compared to random sampling.

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors

In this paper, we propose a phase-driven Q-learning based dynamic reliability management (DRM) technique for multi-core processors to solve DRM problems of maximizing the processor performance subject to a large class of reliability constraints by turning ON/OFF cores and dynamic voltage frequency scaling. Our technique utilizes the existing methods to detect program phases (i.e. [17]) and learns (rather than obtaining at the off-line stage) the optimal configuration of the multi-core processor for each phase. Our technique outperforms the existing learning-based DRM methods in managing programs with highly diverse phases. Our proposed technique is evaluated by solving a DRM problem in 3D CPUs of maximizing processor performance subject to the electromigration induced power delivery network reliability constraint. Compared to the latest Q-learning based DRM technique [11], our method can achieve more than 1.3× improvement in performance with 77% memory savings.

TSV-Based 3-D ICs: Design Methods and Tools

Vertically integrated circuits (3-D ICs) may revitalize Moore’s law scaling which has slowed down in recent years. 3-D stacking is an emerging technology that stacks multiple dies vertically to achieve higher transistor density independent of device scaling. They provide high-density vertical interconnects, which can reduce interconnect power and delay. Moreover, 3-D ICs can integrate disparate circuit technologies into a single chip, thereby unlocking new system-on-chip architectures that do not exist in 2-D technology. While 3-D integration could bring new architectural opportunities and significant performance enhancement, new thermal, power delivery, signal integrity and reliability challenges emerge as power consumption grows, and device density increases. Moreover, the significant expansion of CPU design space in 3-D requires new architectural models and methodologies for design space exploration (DSE). New design tools and methods are required to address these 3-D-specific challenges. This keynote paper focuses on the state of the art, ongoing advances and future challenges of 3-D IC design tools and methods. The primary focus of this paper is TSV-based 3-D ICs, although we also discuss recent advances in monolithic 3-D ICs. The objective of this paper is to provide a unified perspective on the fundamental opportunities and challenges posed by 3-D ICs especially from the context of design tools and methods. We also discuss the methodology of co-design to address more complicated and interdependent design problems in 3-D IC, and conclude with a discussion of the remaining challenges and open problems that must be overcome to make 3-D IC technology commercially viable.