Zohreh R. Hesabi

Self-Standing Crystalline TiO2 Nanotubes/CNTs Heterojunction Membrane: Synthesis and Characterization

In the present study, we report for the first time synthesis of TiO(2) nanotubes/CNTs heterojunction membrane. Chemical vapor deposition (CVD) of CNTs at 650 °C in a mixture of H(2)/He atmosphere led to in situ detachment of the anodically fabricated TiO(2) nanotube layers from the Ti substrate underneath. Morphological and structural evolution of TiO(2) nanotubes after CNTs deposition were investigated by field- emission scanning electron microscopy (FESEM), glancing angle X-ray diffraction (GAXRD), and X-ray photoelectron spectroscopy (XPS) analyses.

Flexible MoS2 Field-Effect Transistors for Gate-Tunable Piezoresistive Strain Sensors

Atomically thin molybdenum disulfide (MoS2) is a promising two-dimensional semiconductor for high-performance flexible electronics, sensors, transducers, and energy conversion. Here, piezoresistive strain sensing with flexible MoS2 field-effect transistors (FETs) made from highly uniform large-area films is demonstrated. The origin of the piezoresistivity in MoS2 is the strain-induced band gap change, which is confirmed by optical reflection spectroscopy. In addition, the sensitivity to strain can be tuned by more than 1 order of magnitude by adjusting the Fermi level via gate biasing.

Tunneling characteristics in chemical vapor deposited graphene–hexagonal boron nitride–graphene junctions

Large area chemical vapor deposited graphene and hexagonal boron nitride was used to fabricate graphene–hexagonal boron nitride–graphene symmetric field effect transistors. Gate control of the tunneling characteristics is observed similar to previously reported results for exfoliated graphene–hexagonal boron nitride–graphene devices. Density-of-states features are observed in the tunneling characteristics of the devices, although without large resonant peaks that would arise from lateral momentum conservation. The lack of distinct resonant behavior is attributed to disorder in the devices, and a possible source of the disorder is discussed.

Cleaning graphene with a titanium sacrificial layer

Graphene is a promising material for future electronic applications and chemical vapor deposition of graphene on copper is a promising method for synthesizing graphene on the wafer scale. The processing of such graphene films into electronic devices introduces a variety of contaminants which can be difficult to remove. An approach to cleaning residues from the graphene channel is presented in which a thin layer of titanium is deposited via thermal e-beam evaporation and immediately removed. This procedure does not damage the graphene as evidenced by Raman spectroscopy, greatly enhances the electrical performance of the fabricated graphene field effect transistors, and completely removes the chemical residues from the surface of the graphene channel as evidenced by x-ray photoelectron spectroscopy.

Synthesis and Growth Mechanism of Thin-Film TiO2 Nanotube Arrays on Focused-Ion-Beam Micropatterned 3D Isolated Regions of Titanium on Silicon

In this paper, the fabrication and growth mechanism of net-shaped micropatterned self-organized thin-film TiO2 nanotube (TFTN) arrays on a silicon substrate are reported. Electrochemical anodization is used to grow the nanotubes from thin-film titanium sputtered on a silicon substrate with an average diameter of ~30 nm and a length of ~1.5 μm using aqueous and organic-based types of electrolytes. The fabrication and growth mechanism of TFTN arrays from micropatterned three-dimensional isolated islands of sputtered titanium on a silicon substrate is demonstrated for the first time using focused-ion-beam (FIB) technique. This work demonstrates the use of the FIB technique as a simple, high-resolution, and maskless method for high-aspect-ratio etching for the creation of isolated islands and shows great promise toward the use of the proposed approach for the development of metal oxide nanostructured devices and their integration with micro- and nanosystems within silicon-based integrated-circuit devices.

Forming-free resistive switching with low current operation in graphene-insulator-graphene structures

Graphene as a conducting electrode has attracted significant attention due to its low sheet resistance, high flexibility and high transparency [1]. Recently, high out-of-plane resistance of graphene has been utilized to reduce the operating current in metal oxide based resistive memories (RRAMs) [2]. However, this report also indicates that the high out-of-plane resistance of graphene contributes to the requirement of high-voltage forming (6 V) [2]. Since the forming step requires significantly higher voltage compared to regular set/reset operations, elimination of the forming step while maintaining the low-current operability is important for graphene RRAMs.In this work we demonstrate forming-free resistive switching in graphene-insulator-graphene (G-I-G) structures with graphene used as both top and bottom electrodes.

Dual-gated field-effect transistors made from wafer-scale synthetic few-layer molybdenum disulfide

Molybdenum disulfide (MoS2) has recently received significant attention because of its interesting thickness-dependent properties and its potential as a semiconducting substitute to graphene [1,2]. Most of the studies so far have focused on small (<; 100 microns) exfoliated MoS2 flakes [1-3]. For manufacturable electronics, it is essential to have large-area material that is compatible with standard fabrication processes for high yield and reproducibility. Though significant progress has been achieved using chemical vapor deposition (CVD) [4,5], the formation of high-quality wafer-scale MoS2 of controlled thickness is still a challenge.