Zusing Yang

Pattern dependent plasma charging effect in high aspect ratio 3D NAND architecture

Pattern dependent charging effect is explored in this study. Due to increased film thickness in 3D NAND structure, a derivative problem-the plasma-induced charging damage is enhanced during high aspect ratio (HAR) etching. In this paper, several effective methods are demonstrated to alleviate the impact of profile distortion due to charging effect while etching high aspect ratio (>14) trenches.

Investigation of shape etching on multi-layer SiO 2 /poly-Si for 3D NAND architecture

This paper describes a simple and systematic etching approach for the preparation of smooth vertical bit line (BL), stacked with multiple layers of SiO2 (OX) and poly-Si (PL) films for the use in three-dimensional vertical gate (3DVG) NAND flash application. A successful shape evolution from tapered to acceptable BL profile with sub-10 nm critical dimension (CD) difference between bottom and top PL layers is performed by a recipe consisting of etch-trim-etch processing steps. This novel etch sequence is more advantageous than that of traditional simultaneous etch-deposition process for controlling profile shape of the multi-layer stack in the 3D NAND flash manufacturing.

Reduction of wafer arcing during high aspect ratio etching

We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.

Investigations on elimination of plasma-induced Si substrate damage for 3D NAND fabrication

This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited unless necessary. The elimination of Si substrate damage is also confirmed with surface layer removal process. The damaged-layer is removed by Si recess procedure, and a healthy Si substrate can be obtained.

Novel hybrid 3D NAND flash memory containing vertical-gate and gate-all-around structures

A novel three-dimensional (3D) NAND structure containing both vertical gate (VG) framework and gate-all-around (GAA) cell structure is innovated and demonstrated. It is fabricated on alternating layers of silicon dioxide (OX) and polysilicon (PL) by using 43nm technology. To our knowledge, one of the major advantages of the novel structure is the smaller cell unit footprint than vertical channel (VC) designs; it also provides storage density comparable with VC by the use of much less cell stacks. Furthermore, GAA cell structure is expected to contain better program/erase characteristics than VG due to curvature effect. In this paper, we discuss some of the most critical processes for fabrication of such 3D NAND flash with VG-GAA designs.