Kuang-Chao Chen

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, and for the first time the “Z-interference” between adjacent vertical layers is studied. The proposed buried-channel VG NAND allows better X, Y pitch scaling and is a very attractive candidate for ultra high-density 3D stackable NAND Flash.

A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory

Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

Sub-30nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory window is also larger than the bulk planar devices due to the tri-gate structure that enhances the electric field during programming/erasing. However, a fair percentage of devices contain grain boundaries with poorer S.S. and gm. Interestingly, this only affects the DC characteristics but does not impact the memory window. Furthermore, grain boundaries do not increase the random telegraph noise. The most serious drawback of grain boundaries is the impact on self-boosting window caused by junction leakage. A sub-30 nm TFT BE-SONOS NAND device with MLC capability and good retention is demonstrated

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the worlds first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

A novel p-channel NAND-type flash memory with 2-bit/cell operation and high programming throughput (> 20 MB/sec)

A novel p-channel NAND-type non-volatile flash memory using nitride-trapping device is presented. The p-channel device is programmed by very efficient band-to-band tunneling hot electron (BBHE), and erased by self-converging channel hole tunneling. An ultra-thin bandgap engineered ONO tunneling dielectric as presented in H. T. Lue et al. (2005) is adopted to achieve efficient hole-tunneling erase at high electric field, but yet good data retention at low field. The operation of physically 2-bit/cell NAND-type architecture with depletion mode device (VT > 0) is illustrated. Excellent P/E cycling endurance, data retention and read disturb immunity are demonstrated. This new non-volatile p-channel memory device is capable of very high-programming throughput (> 20 MB/sec) suitable for data Flash application

A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

For the first time, a successful TFT NAND-type flash memory is demonstrated using a low thermal budget process suitable for stacking the memories. A TFT-SONOS device using bandgap engineered SONOS (BE-SONOS) (Lue, et al. 2005) with fully-depleted (FD) poly silicon (50 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.18/0.09 mum) with good DC performance are achieved, owing to the good control capability of the tri-gate FD structure. Successful NAND array functions are demonstrated, with more than 1 muA read current for a 16-string NAND array and good program disturb immunity. This new device also shows good endurance and data retention, and negligible read disturb. These results are very encouraging for future 3D flash memory

A High-Speed BE-SONOS NAND Flash Utilizing the Field-Enhancement Effect of FinFET

Theoretical calculation indicates that when the fin width is comparable to the EOT of the ONO, the bottom oxide electric field around the fin tip is significantly increased, resulting in the enhanced program/erase efficiency. We also discover that the non-uniform injection along the fin changes DC characteristics (S.S. and gm) during program/erase, and the effective channel width of FinFET SONOS is only around the fin tip. We integrate BE-SONOS in a body-tied FinFET structure with a very small fin width (<20 nm), and demonstrate a high-speed NAND Flash (<20 musec programming time and <2 msec erasing time for a 5 V memory window). The present work provides not only physical insights into the operation mechanisms of FinFET SONOS-type devices, but also a new design method for high-speed NAND Flash.

Reliability Model of Bandgap Engineered SONOS (BE-SONOS)

Reliability properties of bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) are extensively studied. First, the erase mechanism of BE-SONOS is confirmed as substrate hole tunneling through the ultra-thin ONO tunneling dielectric. Next, very long-term (>3,000 hours) high-temperature baking data (from 150 to 250degC) for various programmed/erased states and cycling history are collected and analyzed for a thorough understanding of the retention property. By transforming retention data (VFB-time) into de-trapping current (J) and modeling its dependence on electric field and temperature, the long-term retention of various programmed states are consistently and accurately predicted. This modeling technique avoids the ambiguity of the common Arrhenius plot, and is useful for developing other predictive models too. We have shown that BE-SONOS surpasses the 10-year 85degC storage criterion for Flash memory applications

Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)

The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary to suppress the parasitic leakage path and avoid the abnormal subthreshold current behavior. Second, the edge fringing field effect significantly changes the P/E speed and degrades the incremental-step-pulse programming (ISPP) slope from ideal value (=1). The complexity of the edge fringing field cannot be modeled by simple 1D tunneling, and by using 3D simulation we found that the edge fringing field greatly degrades the tunnel oxide electric field especially after electrons are programmed into the channel. Moreover, because of edge fringing field effect more charge injection is required to obtain the same memory window when the device is scaled. We propose an analytical ISPP model. A field enhancement factor (FE) is introduced, and the FE gradually decreases with electron injection while Vt gets higher. Through this model the ISPP programming of various STI structures can be well understood. Finally, we find that the self-boosting program disturb window is proportional to the ISPP slope.

Study of Local Trapping and STI Edge Effects on Charge-Trapping NAND Flash

Unlike the floating gate Flash device, charge-trapping (CT) devices store charges locally and are thus profoundly affected by non-uniform injection effect. The characteristics of a CT device are dominated by the local minimum-Vt region along the channel width. We have analyzed various STI structures including raised-STI, recessed-STI, and near-planar structures, and found that the program/erase characteristics are strongly impacted by the STI corner geometry due to local field enhancement (FE) and non-uniform injection effects. Moreover, both gm and S.S. vary during program/erase and thus increase programming/erasing complexity. The read disturb, program disturb, and retention characteristics are examined in detail. These conclusions apply to all CT devices.