Stefan Lai

Current status of the phase change memory and its future

With the increasing challenge of scaling floating gate nonvolatile memory technology to beyond 65 nm, alternative memory technologies are being investigated. Chalcogenide based phase change memory (R. Neale et al, Electronics, p56-60, 1970) is one of the alternative memory candidates. In this review, the physics and operation of phase change memory are first presented, followed by a discussion of the current status of development. Finally, the scaling capability of the technology is presented. The scaling projection shows that there is no physical limit to scaling down to the 22 nm node, with a number of technical challenges being identified.

OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications

This paper discusses the development status of the memory cell element of OUM (Ovonic Unified Memory) - a chalcogenide-based, phase-change nonvolatile semiconductor memory technology at the 180 nm technology node. The device structure and characterization of the memory element will be reviewed. The key characteristics of the technology will be discussed for ultra-high density, low voltage, high-speed programming, high cycle count, high read speed, and competitive cost structure nonvolatile memory for stand alone and embedded applications. This technology is inherently radiation resistant and is bit byte or word programmable without the requirement of Flash-like block erase. Low voltage and energy operation make OUM an attractive candidate for mobile applications.

Electrical properties of nitrided-oxide systems for use in gate dielectrics and EEPROM

The electrical properties of nitrided oxide systems as a function of process conditions were examined. In terms of electron trapping, the observed results can be explained by the existence of two different traps: intrinsic and high field generated traps. The densities of these traps are determined by the nitridation condition and subsequent heat cycles. The lowest density of electron traps was observed in an annealed nitrided oxide (NO). The results also have implications for radiation damage and hot electron channel degradation in thin gate dielectrics. Under very high electric fields, destructive breakdowns were observed for nitrided oxide, probably due to the absence of electron traps. Such breakdowns restrict the design of EEPROMs using such dielectrics.

Flash memories: where we were and where we are going

This paper examines why stacked gate ETOX/sup TM/ is the highest volume flash memory technology up to now. Looking into the future, technologies for flash memories will become more diversified. Multi-level storage technology will be prevalent and plays a dominant role in lowering bit cost. Flash memory card is emerging as a new market segment, and there is increasing demand to integrate high performance logic with flash.

Non-volatile memory technologies: The quest for ever lower cost

Growth of flash memory business over last 20 years was driven by never ending reduction of memory cost through Moores Law and innovations, and the quest for ever lower cost will continue for many years to come. This review begins with a brief summary of trend of flash memory cost reduction up to now. Then some of the improvement efforts on existing technologies reported by industry will be discussed. NAND flash will continue to be the cost reduction driver in next few years but will face increasing level of difficulties. Innovations will enable the trend to continue. For longer term, industry is developing new memory technologies that have promise to deliver ever lower cost. Some more mature new technology concepts will be discussed in this review. General direction is to go to multi-layer memories with multi-level cell capabilities. There are also alternative approaches like probe based storage. Enhancement from system level solution will help existing technologies as well as facilitating introduction of new technologies. It is expected that products from few new technologies will take off in coming years to enable continuation of cost reduction of non-volatile memories, meeting insatiable demand of existing devices for more memory capacity at lower cost, as well as creating new devices and new markets.

A novel memory cell using flash array contactless EPROM (FACE) technology

A single transistor flash memory cell which utilizes channel hot electron injection for programming and Fowler-Nordheim tunneling for erase is described. This flash memory technology uses a buried N/sup +/ bitline to connect the memory transistors rather than metal and contacts. Elimination of contacts results in a 45% cell area shrink of the conventional ETOX cell (based on 1.0 mu m design rules). A 4.48 mu m/sup 2/ cell area is also realized by using a 0.8 mu m technology. In addition to this cell scalability, the diffusion corner induced erase threshold bimodality can be reduced due to the intrinsic stripe geometries in the memory array. Furthermore, this contact/metal related layout rules can be relaxed, which allows this contactless approach to be extended to future generations without requiring complicated contact processing. Hence, the flash array contactless EPROM (FACE) technology lends itself to a very compact cell as well as a more manufacturable process.<<ETX>>

Comparison and trends in today's dominant E 2 technologies

This paper reviews the three dominant E2technologies today, namely the two floating gate approaches of thin tunnel oxide and oxide of textured poly and the dual dielectric approach of MNOS. It evaluates each approach with respect to cell design, operation, manufacturability, compatibility with established process technologies and reliability. It follows with a comparison of the technologies in the areas of development entry cost, scaling and reliability. After a review of the market place, this paper concludes with a projection of the requirements of E2technologies to support full function, commodity E2memories E2PROM as well as low cost microcontrollers and ASIC (Application Specific Integrated Circuits).

Design of an E 2 PROM memory cell less than 100 square microns using 1 micron technology

In this paper, the design of a state of the are E2PROM memory cell is presented. This memory cell is being incorporated in a third generation electrically erasable non-volatile memory technology based on 1 µm lithography. The 1 µm lithography is being used aggressively in the design of the memory cell to achieve the highest feature density. The memory cell is 13.5 µm in Y dimension and 7 µm in X dimension. The basic philosophy of the design is the maximization of coupling ratio, both in program and erase. This allows the use of a thicker tunnel oxide to give the highest yield and reliability. The tunnel oxide area is defined by two masking steps instead of one in competitive designs to minimize the drain capacitance, giving higher erase coupling ratio and thus a larger window. It will be shown that this is a very solid and reliable cell that will be used in high density E2PROMs.

A novel Bi-stable 1-transistor SRAM for high density embedded applications

A 1-transistor SRAM on bulk substrate is presented. The device is fabricated in 28 nm foundry baseline process with an additional buried N-well (BNWL) implant. The unit cell consists of a lateral MOS for memory access operations and intrinsic vertical open-base bipolar structures for self-latch function. The bit cell operation and the disturb immunity are verified at high temperature. Using 28 nm design rules, a unit cell size of 0.025 μm2 is achieved, offering 80% cell size reduction over 6T-SRAM and providing comparable power and performance.