A. Abuelgasim

Reduced microwave attenuation in coplanar waveguides using deep level impurity compensated Czochralski-silicon substrates

We show that deep level doping of Czochralski-grown silicon wafers is capable of providing high resistivity handle wafers suitable for radio frequency integrated circuits. Starting from n-type Czochralski silicon wafers having a nominal resistivity of 50 Ω cm, we use ion implantation and subsequent annealing to increase the resistivity of the wafers to over 10 kΩ cm at room temperature. Coplanar waveguides fabricated on implanted wafers show strongly reduced attenuation down to 0.3 dB mm−1 from 0.8 dB mm−1 for un-implanted wafers in the 1–40 GHz range, providing clear evidence that the technique is effective in improving performance of passive devices at GHz range frequencies.

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source-drain (S/D) activation anneal of 30 s at 1100°C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.

Drive Current improvement in vertical MOSFETS using hydrogen anneal

This paper reports a study of the effect of a hydrogen anneal after silicon pillar etch on the electrical characteristics of surround-gate vertical MOSFETs. Electrical results on 120 nm, n-channel, surround-gate vertical MOSFETs show that the hydrogen anneal gives rise to a 30% improvement in drive current in comparison to transistors without the hydrogen anneal. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The hydrogen anneal has little effect on the values of sub-threshold slope and DIBL, with excellent values of 79mV/decade and 45mV/V respectively being achieved. The results are explained by an improved mobility due to a reduction in surface roughness on the silicon pillar sidewall and a gate oxide thinning by the hydrogen anneal.

Improved Drive Current in RF Vertical MOSFETS Using Hydrogen Anneal

This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800°C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors with out the hydrogen anneal. The value of drive current achieved is 250 μA/μm, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H2 anneal is also shown to decrease the OFF-state leakage current by a factor of three.

Fabrication of low loss coplanar waveguides on gold-doped Czochralski-silicon

Coplanar waveguides fabricated on gold-doped Czochralski-silicon show reduced losses. Gold atoms implanted into silicon substrates compensate for background free carriers introduced by impurities in the material. This leads to an increased silicon resistivity which exhibits lower microwave absorption. High frequency measurements in 1-40 GHz range of coplanar waveguides fabricated on gold-doped silicon show attenuation reductions up to 70%, highlighting the benefits of deep level compensation of shallow level impurities in silicon using gold.

Coplanar waveguides on gold-doped high resistivity silicon for 67-GHz microwave application

High resistivity handle wafers suitable for radio frequency integrated circuit application have been achieved through deep level doping compensation technique. Ion implantation and subsequent annealing were used to introduce electrically active gold atoms into silicon resulting in an increase in resistivity up to 70 kOhm-cm from a nominal value of 50 Ohm-cm. At 67GHz, attenuation loss for coplanar waveguides shows a strong reduction from 0.88 dB/mm obtained from un-implanted wafers to 0.3 dB/mm in gold-implanted wafers.