Kanad Mallik

Electrodeposition of metals from supercritical fluids

Electrodeposition is a widely used materials-deposition technology with a number of unique features, in particular, the efficient use of starting materials, conformal, and directed coating. The properties of the solvent medium for electrodeposition are critical to the techniques applicability. Supercritical fluids are unique solvents which give a wide range of advantages for chemistry in general, and materials processing in particular. However, a widely applicable approach to electrodeposition from supercritical fluids has not yet been developed. We present here a method that allows electrodeposition of a range of metals from supercritical carbon dioxide, using acetonitrile as a co-solvent and supercritical difluoromethane. This method is based on a careful selection of reagent and supporting electrolyte. There are no obvious barriers preventing this method being applied to deposit a range of materials from many different supercritical fluids. We present the deposition of 3-nm diameter nanowires in mesoporous silica templates using this methodology.

The structural and electrical properties of thermally grown TiO2 thin films

We studied the structural and electrical properties of TiO2 thin films grown by thermal oxidation of e-beam evaporated Ti layers on Si substrates. Time of flight secondary ion mass spectroscopy (TOF-SIMS) was used to analyse the interfacial and chemical composition of the TiO2 thin films. Metal oxide semiconductor (MOS) capacitors with Pt or Al as the top electrode were fabricated to analyse electrical properties of the TiO2 thin films. We show that the reactivity of the Al top contact affects electrical properties of the oxide layers. The current transport mechanism in the TiO2 thin films is shown to be Poole–Frenkel (P–F) emission at room temperature. At 84 K, Fowler– Nordheim (F–N) tunnelling and trap-assisted tunnelling are observed. By comparing the electrical characteristics of thermally grown TiO2 thin films with the properties of those grown by other techniques reported in the literature, we suggest that, irrespective of the depositio nt echnique, annealing of as-deposited TiO2 in O2 is a similar process to thermal oxidation of Ti thin films.

Enhancement of resistivity of Czochralski silicon by deep level manganese doping

Deep level manganese Mn doping has been used to fabricate very high resistivity single crystal silicon substrates grown by the Czochralski method. The Mn has been introduced by ion implantation with a dose of 10^14 cm^?2 of Mn at 100 keV followed by rapid thermal annealing at 800 °C for 36 s. The resistivity of the wafer is enhanced from 600 ohm cm for the undoped substrate to a maximum of 10 kohm cm for the Mn-doped substrate. The experimental data are corroborated using a theoretical model for doping compensation due to deep level impurities. This level of obtained resistivity is suitable for making silicon on-chip integration of radio frequency devices.

Schottky diode back contacts for high frequency capacitance studies on semiconductors

A technique using large area Schottky diode back contacts has been developed to enable high frequency capacitance studies to be carried out on semiconductors without the need to fabricate high quality ohmic back contacts. This technique will find application for very high resistivity materials or for the characterization of novel semiconductors when a method of producing good ohmic contacts has not been established. In this method a back contact much larger in area than the front contact diode under test is used. It is then found that accurate capacitance-voltage measurements can be made of the ionized doping density and, provided the back contact has sufficient leakage, the built-in potential can also be measured. Such specimens may also be used for characterization using the deep level transient spectroscopy (DLTS) technique and this is demonstrated by obtaining DLTS spectra from very high resistivity silicon specimens containing oxygen precipitates and comparing these to similar spectra obtained from more highly doped material.

Reduced microwave attenuation in coplanar waveguides using deep level impurity compensated Czochralski-silicon substrates

We show that deep level doping of Czochralski-grown silicon wafers is capable of providing high resistivity handle wafers suitable for radio frequency integrated circuits. Starting from n-type Czochralski silicon wafers having a nominal resistivity of 50 Ω cm, we use ion implantation and subsequent annealing to increase the resistivity of the wafers to over 10 kΩ cm at room temperature. Coplanar waveguides fabricated on implanted wafers show strongly reduced attenuation down to 0.3 dB mm−1 from 0.8 dB mm−1 for un-implanted wafers in the 1–40 GHz range, providing clear evidence that the technique is effective in improving performance of passive devices at GHz range frequencies.

A self-aligned silicidation technology for surround-gate vertical MOSFETS

We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120 nm n-channel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DIBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DIBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78 mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained.

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source-drain (S/D) activation anneal of 30 s at 1100°C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.

Semi-insulating silicon for microwave devices

The concept of fully encapsulated, semi-insulating silicon (SI-Si), Czochralski-silicon-on-insulator (CZ-SOI) substrates for silicon microwave devices is presented. Experimental results show that, using gold as a compensating impurity, a Si resistivity of order 400 kΩcm can be achieved at room temperature using lightly phosphorus doped substrates. This compares favourably with the maximum of ~180kΩcm previously achieved using lightly boron doped wafers and is due to a small asymmetry of the position of the two gold energy levels introduced into the band gap. Measurements of the temperature dependence of the resistivity of the semi-insulating material show that a resistivity ~5kΩcm can be achieved at 100°C. Thus the substrates are suitable for microwave devices working at normal operating temperatures and should allow Si to be used for much higher frequency microwave applications than currently possible.

Semi-insulating Czochralski-silicon for Radio Frequency Applications

Deep level manganese doping by ion implantation and rapid thermal annealing have been used for the first time to make very high resistivity Czochralski silicon substrates up to 10 kOmegacm and on the average, this is nearly a ten-fold increase over the resistivity of the undoped starting wafer. The material is ideally suited for making semi-insulating silicon handle wafers for radio frequency silicon devices. Interesting features, like trapping by end-of range defects, out-diffusion and partial activation of Mn dopant atoms have been observed

Fabrication of low loss coplanar waveguides on gold-doped Czochralski-silicon

Coplanar waveguides fabricated on gold-doped Czochralski-silicon show reduced losses. Gold atoms implanted into silicon substrates compensate for background free carriers introduced by impurities in the material. This leads to an increased silicon resistivity which exhibits lower microwave absorption. High frequency measurements in 1-40 GHz range of coplanar waveguides fabricated on gold-doped silicon show attenuation reductions up to 70%, highlighting the benefits of deep level compensation of shallow level impurities in silicon using gold.