A.B. Bhattacharyya

Interface-state characteristics of GaN/GaAs MIS capacitors

Abstract Detailed results of the capacitance voltage, conductance voltage and transient capacitance analysis on GaN/GaAs MIS capacitor are presented. It has been found that the low frequency capacitance rises for deep-depletion biases for both n - and p -type GaAs. Transient capacitance analysis has resulted in bulk life time of a few nanosec which is expected for direct band gap semiconductors like GaAs. The interface state density distribution as obtained from the conductance technique showed a rise in the interface state density around 0.30 eV below E c and 0.55 eV above E ν of GaAs. The minimum interface state density is around 8 × 10 10 /cm 2 eV.

The nature of intrinsic hole traps in thermal silicon dioxide

The energy and spatial distribution of intrinsic hole traps in dry thermal silicon dioxide have been determined. Thermal detrapping was used for the determination of energy levels of the traps and the etch‐back technique was used to find the spatial location of the traps. These traps are distributed in energy from 1.0 to 1.5 eV with respect to the valence band edge of the silicon dioxide. Their centroid is located at approximately 120 A from the Si–SiO2 interface. Results of various postoxidation annealing treatments show that the density of traps is significantly dependent on the process conditions. Like fixed charge Qf, these traps seem to be related to the lattice imperfections in SiO2 near the interface; however, the hole trap density and Qf vary in opposite directions due to the process changes. N2 annealing increases the trap density and O2 annealing, which reduces the hole trap density, increases the electron trap density in SiO2. Based on these results we support the trivalent silicon model for th...

Analytical Model for Optimum Signal Integrity in PCB Interconnects Using Ground Tracks

In this paper, we present analytical models for line impedance and the coupling coefficient in the presence of additional ground tracks. We use a variational analysis combined with the transverse transmission-line technique to model interconnect lines guarded by ground tracks. Using the proposed model, it would be possible for designers to reduce crosstalk in coupled lines and obtain desired line impedance, thereby ensuring optimum signal integrity. The results obtained are verified by full-wave simulations and measurements performed on a vector network analyzer. The proposed model may find applications in the design and analysis of high-speed interconnects.

SPICE simulation of surface acoustic wave interdigital transducers

Surface Acoustic Wave (SAW) devices, are not normally amenable to simulation through circuit simulators. In this letter, an electrical macromodel of Masons Equivalent Circuit for an interdigital transducer (IDT) is proposed which is compatible to a widely used general purpose circuit simulator SPICE endowed with the capability to handle negative capacitances and inductances. Illustrations have been given to demonstrate the simplicity of ascertaining the frequency and time domain characteristics of IDT and amenability to simulate the IDT along with other external circuit elements.<<ETX>>

Matching properties of linear MOS capacitors

Abstract The matching property of MOS capacitors has been studied in accordance with well established statistical principles and on the basis of the experimentally generated data. Various random error mechanisms have been studied in a systematic manner. For edge-related errors, structures with approximately equal area but differing perimeters have been considered. Similarly, for corner-related errors, structures having approximately the same area and perimeter but a different number of corners have been studied. Some empirical relationships have been obtained. For the presently considered dimensions and technology, normalized random error in capacitor-ratio has been observed to have (i) an inverse square-root dependence upon the capacitor-area; (ii) a linear dependence upon the perimeter-to-area ratio; and (iii) a very weak dependence, n 1 6 , upon the capacitor-ratio n . “Statistically highly significant” improvement in matching has been observed for hitherto unreported structure in which photolithographically defined corners are completely avoided. Application of the above “corner-less” configuration would result in a considerable saving of the capacitor-area in switched-capacitor, A/D and D/A converter applications. For realizing small real ratios, use of rectangular and ring-type structures is proposed. “Statistically significant” improvement in capacitor-matching has been obtained for such structures even though the perimeter-to-area ratio ( P / A ) of such structures is greater than the corresponding square-geometry ones.

Delay-time sensitivity in linear RC tree

The study of RC networks is important to understand digital MOS integrated circuits. Several authors studied these networks from the point of view of bounds on voltage waveform [1], [2], signal delay [3], etc. Wyatt [4] developed a qualitative theory of RC meshes having monotone elements. He showed that for a monotone exitation u(t) , the sensitivity of the output node voltage of a nonleaky line is monotonic due to any conductance on the line.

Characteristic Impedance of a Microstrip-Like Interconnect Line in Presence of Ground Plane Aperture

We propose new empirical expressions for the characteristic impedance of a microstrip-like interconnect line in presence of ground plane aperture. The existing characteristic impedance expressions are modified so as to include the effect of the ground plane aperture. The variation in the characteristic impedance vis-a-vis the aperture size is established. The proposed expressions are general and valid for a range of dielectric materials concerning MICs, RFICs, and PCBs. The results are validated by measurements performed on a vector network analyzer.

Switching properties of epitaxial planar transistors operating in saturation

Abstract In an epitaxial transistor operating in saturation, charge is stored not only in the active and passive base regions but also in the region bounded between the collector junction and n - n + interface. The saturation operation of a transistor switch is characterized by a single most fundamental parameter, the saturation time constant, which may be related to the intrinsic physical structure of the transistor. In this paper, an attempt has been made to correlate the saturation behaviour of an epitaxial planar transistor with its physical structure. The analysis takes into account the effects of n - n + interface in the collector and the retarding-accelerating built in field for the minority carriers in the base, both of which so far have been subject to gross simplifications. The theoretical conclusions have been verified experimentally for some typical epitaxial planar transistors.

Approximation to impurity atom distribution from a two-step diffusion process

The most commonly used diffusion process in planar technology is known as two-step diffusion, and the impurity atom profile is given by an integral. An approximation is suggested for such a profile which is simpler and accurate enough to be used in device characterization. It is seen that the built-in field resulting from two-step diffusion can be approximated as linearly varying with distance.

On-line extraction of model parameters of a long buried-channel MOSFET

A buried-channel depletion MOS transistor has an implanted neutral conducting channel between the source and drain due to which the device works in a variety of modes such as accumulation, accumulation-depletion, depletion, inversion-depletion, inversion, etc., and presents a more complex structure than an enhancement-mode device. For precise circuit simulation, accurate and on-line extraction of model parameters has assumed significant importance. It is found that representing the implanted buried channel by an equivalent box with average doping and junction depth gives a convenient trade-off between simplicity in modeling and accuracy in device characterization. The present work proposes a method of deriving the necessary model parameters through the measurement of a single device parameter, namely drain conductance under different operating conditions. The on-line measurements carried on a boron-implanted relatively long buried-channel MOSFET have been used to predict the best box for the profile and give other model parameters necessary for circuit simulation. It is shown that the method is most insensitive to measurement conditions compared to other techniques.