A. Bajolet

Characterization and Modeling of Transistor Variability in Advanced CMOS Technologies

This paper aims at reviewing the results that we have obtained during the last ten years in the characterization and modeling of transistor mismatch in advanced complementary metal-oxide-semiconductor (CMOS) technologies. First, we review the theoretical background and modeling approaches that are generally employed for analyzing and interpreting the mismatch results. Next, we present the experimental procedures and methodologies that we used for characterizing the transistor matching. Then, we discuss typical matching results that were obtained on modern CMOS technologies and analyze the main variability (mismatch) sources. Finally, we conclude by summarizing our findings and giving some recommendations for future technologies.

Three-dimensional 35 nF/mm/sup 2/ MIM capacitors integrated in BiCMOS technology

Decoupling applications require high capacitance values. To optimize the chip performances, it appears particularly interesting to integrate them directly in interconnect levels, especially in BiCMOS technology. In order to reach this goal and minimize the area occupied by such devices, three-dimensional MiM capacitors have been introduced with different dielectrics: Ta/sub 2/O/sub 5/ deposited by MOCVD and A1/sub 2/O/sub 3/ by ALD. Thus, high capacitance density of 35nF/mm/sup 2/ has been reached. Through comparison between planar and three dimensional (3D) MIM capacitor characterization, it has been demonstrated that 3D MIM capacitor, named high density trench capacitor (HiDTC), architecture is a very promising candidate to integrate such high capacitance values.

New methodology for drain current local variability characterization using Y function method

Y function is well known to overcome the influence of source/drain series resistance (Rsd) in MOSFETs. In this work we present a new methodology for drain current local variability characterization using Y function method. Thus, we show that the study of Y function statistical variability permits the extraction of threshold voltage (VTH) and current gain factor (β) local variability without the influence of Rsd values. We also demonstrate a simple drain current local variability model taking into account the influence of Rsd and its variability in strong inversion regime. This new VTH and β extraction method, and drain current variability model were applied with success to advanced FDSOI and Bulk devices with different dimensions.

Low-Frequency Series-Resistance Analytical Modeling of Three-Dimensional Metal–Insulator–Metal Capacitors

This paper discusses the optimization of series resistance of nonplanar metal-insulator-metal capacitor, i.e., an original 3-D capacitor with a capacitance density of 35 nF/mm2, used in very large scale integration. A fully analytical and physically based model of its series resistance versus material and geometrical parameters has been developed, in excellent agreement with both 3-D numerical simulations and experiments. Based on the modeling results, possible design strategies of series-resistance reduction are suggested; showing a reduction of the series resistance by approximately a factor of four, without any degradation of the capacitance density

Drain current variability in 45nm heavily pocket-implanted bulk MOSFET

Pocket architecture is a useful technique to eliminate short channel effects to provide smaller transistors sizes. However, it has been shown that it has an important drawback on mismatch. In this paper, the drain-current mismatch σ(ΔId/Id) is characterized for transistors without pockets and for heavily pocket-implanted transistors. These characterizations are performed from linear to saturation regime. A drain-current mismatch model as a function of drain voltage valid from weak to strong inversion region is also presented. For the first time, the drain current mismatch parameter is analyzed from linear to saturation regime for pocket devices. Thus, a comparison between transistors without pocket and transistors with pocket is performed and an important drain-current mismatch enhancement in the latter case is reported and discussed.

Impact of TiN Plasma Post-Treatment on Alumina Electron Trapping

Three-dimensional architecture appears today to be essential for the next high-density metal-insulator-metal (MIM) capacitor generation. Thus, the classical physical vapor deposition method usually used for the electrode deposition must be replaced by more conformal deposition methods, like chemical vapor deposition (CVD) method. In this paper, trapping phenomenon of MIM capacitors using CVD-TiN for electrodes and atomic layer deposition Al2O3 for insulator is studied, when integrated in planar and in 3-D MIM devices. In particular, we demonstrate the correlation between the plasma post-treatment (PT) applied to the CVD-TiN layer to ensure its low resistivity and the charge trapping in the alumina. Moreover, while applying the Di Maria method to those MIM structures, we demonstrate that charges trapped are electrons, which are located near the metal/insulator interfaces. Based on previous paper, an explanation of the origin of this trapping phenomenon is also proposed. Finally, we demonstrate that the plasma PT does not penetrate correctly into the trenches, suggesting that CVD method for the TiN electrode deposition is not suitable for high-aspect-ratio 3-D devices.

Mismatch trends in 20nm gate-last bulk CMOS technology

In this work Vt and β mismatch for the 20 nm Gate-last bulk CMOS technology are investigated for the first time. Our results indicate that the 20 nm Gate-last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-first counterpart. Furthermore, the evolution of the Vt and β mismatch parameters, iA_ΔVt and iA_Δβ/β, is analyzed as a function of EOT (Tox) from the 90 nm technology node down to the 20 nm technology node. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot iA_ΔVt vs EOT is observed from the 28 nm Gate-first technology, with such offset approaching zero for the 20 nm Gate-last technology node. This indicates evidence of a huge decrease in the mismatch contribution of the gate material.

Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance

The work presented in this paper investigates the possibility of replacing a Lateral Drain Extended MOS (LDEMOS) SOI transistors by a cascode configuration to improve the electrical mismatch performance. The cascode connection of two MOS devices is known to sustain as high drain voltage as LDEMOS SOI transistors and offers the same mismatch robustness of Silicon On Insulator (SOI) MOS transistors. The individual mismatch constants associated to Vt (iA_Δvt), β (iA_Δβ/β) and Id (iA_ΔId/Id) for the presented cascode configuration are shown to have similar values to those reported for individual MOS devices.

New capacitor parametric test methodology for process issues control

This paper describes a new measurement methodology based on LCR-meter tan(delta) measurement versus frequency. Directly integrated during parametric test, it gives information on capacitors key parameters like dielectric relaxation, potential dielectric contamination, extrinsic conduction, series resistance and process issue. The methodology is validated, thanks to the Kramers-Kronig relations, traditional I(V) measurements and series resistance model. Finally a practical example of a 3D MIM capacitor is studied.

High-K dielectric deposition in 3D architectures: The case of Ta2O5 deposited with metal–organic precursor TBTDET

Abstract New applications in microelectronics need the integration of high capacitance devices. One way of this development is the integration of capacitors with 3D architecture such as trench fields. The challenge is then to deposit the dielectric material in a highly conformal way within trenches showing high aspects ratios. We have studied and modeled the conformality and the loading effect of Ta 2 O 5 deposited by MOCVD in an analytical way.