Julien Rosa

A New Technique to Extract the Source/Drain Series Resistance of MOSFETs

This letter demonstrates a new technique to extract the source/drain series resistance of MOSFETs. Unlike the well-known total resistance techniques, Rsd is extracted in a way that the result is insensitive to effective length and mobility variations. The technique has been successfully applied to 45-nm bulk and fully depleted SOI MOSFETs with high-κ and metal gate, having channel length down to 22 nm. The technique provides a high accuracy and allows fast measurements and statistical analysis.

New methodology for drain current local variability characterization using Y function method

Y function is well known to overcome the influence of source/drain series resistance (Rsd) in MOSFETs. In this work we present a new methodology for drain current local variability characterization using Y function method. Thus, we show that the study of Y function statistical variability permits the extraction of threshold voltage (VTH) and current gain factor (β) local variability without the influence of Rsd values. We also demonstrate a simple drain current local variability model taking into account the influence of Rsd and its variability in strong inversion regime. This new VTH and β extraction method, and drain current variability model were applied with success to advanced FDSOI and Bulk devices with different dimensions.

Mismatch trends in 20nm gate-last bulk CMOS technology

In this work Vt and β mismatch for the 20 nm Gate-last bulk CMOS technology are investigated for the first time. Our results indicate that the 20 nm Gate-last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-first counterpart. Furthermore, the evolution of the Vt and β mismatch parameters, iA_ΔVt and iA_Δβ/β, is analyzed as a function of EOT (Tox) from the 90 nm technology node down to the 20 nm technology node. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot iA_ΔVt vs EOT is observed from the 28 nm Gate-first technology, with such offset approaching zero for the 20 nm Gate-last technology node. This indicates evidence of a huge decrease in the mismatch contribution of the gate material.

New access resistance extraction methodology for 14nm FD-SOI technology

In this work, an improved methodology of access resistance extraction is proposed and applied on dedicated Kelvin test structures from a FD-SOI 14 nm technology. The use of this new approach and these test structures allow to confirm that the parasitic resistance of advanced MOSFET is highly dependent of the gate voltage. This explains the impossibility to decorrelate intrinsic and access components using Y function method for very small gate length transistors. A simple phenomenological model for MOSFETs access resistance is proposed and validated at the drain current level.

Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance

The work presented in this paper investigates the possibility of replacing a Lateral Drain Extended MOS (LDEMOS) SOI transistors by a cascode configuration to improve the electrical mismatch performance. The cascode connection of two MOS devices is known to sustain as high drain voltage as LDEMOS SOI transistors and offers the same mismatch robustness of Silicon On Insulator (SOI) MOS transistors. The individual mismatch constants associated to Vt (iA_Δvt), β (iA_Δβ/β) and Id (iA_ΔId/Id) for the presented cascode configuration are shown to have similar values to those reported for individual MOS devices.

Improved precision methodology for access resistance extraction using Kelvin test structures

An improved methodology for MOSFETs access resistance extraction using Kelvin test structures is presented. By a drastic reduction of the influence of the device stochastic variations, along with an improved methodology for sub 50nm technologies, one site fast inline extraction can be performed with precision, allowing measurement of systematic series resistance variations on wafer.

Transport characterisation of Ge pMOSFETS in saturation regime

The limiting carrier velocity concept allowing the determination of the nature of transport is used for the first time in Ge channel MOSFET. The limiting carrier velocity extracted on bulk germanium (Ge) pMOSFET is studied versus temperature. A drift-diffusion dominated transport is demonstrated despite the good transport quality of germanium devices down to 60 nm.

New method for non destructive snap-back characterization in multi-finger power MOSFETs

A non destructive conductance-based electrical characterization method of the snap-back phenomenon has been implemented to investigate multi-finger power MOSFETs. The context of our study is presented, then the specific test structures and the measurement methodology are shown. The robustness and repeatability of our approach is demonstrated on a variety of power MOSFETs regarding to some technological parameters. Comparisons between our results and the ones issued from a destructive characterization are also drawn. The temperatures influence on snap-back is evidenced as well as the measurements repeatability.

Impact of access resistance on New-Y function methodology for MOSFET parameter extraction in advanced FD-SOI technology

In this work, an upgraded version of the so called New Y function [1] MOSFET parameter extraction methodology is proposed, taking the impact of access resistance into account. This new approach emphasizes the importance of considering access resistance variation with gate bias when extracting MOSFET parameters.

Silicon thickness monitoring strategy for FD-SOI 28nm technology

The silicon thickness (Tsi) fluctuation monitoring on FD-SOI 28nm technology process is addressed by 2 different electrical characterization techniques. The first, capacitive, is adapted to within wafer variations and lot/wafer variations monitoring. The second, using the Idsat sensitivity to the Tsi in an addressable transistors array, allows to measure the local variations in the range of few tens of microns.