A. Ortiz-Conde

A review of recent MOSFET threshold voltage extraction methods

The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical implementation of the several methods presented is illustrated and their performances are compared under the same challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk MOSFET with state-of-the-art short-channel length, and an experimental n-channel a-Si:H thin film MOSFET. 2002 Elsevier Science Ltd. All rights reserved.

Anomalous leakage current in LPCVD PolySilicon MOSFET's

The anomalous leakage current ILin LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of ILon the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce IL, and indicates when the back-surface leakage component is significant.

New procedure for the extraction of basic a-Si:H TFT model parameters in the linear and saturation regions

Abstract A new procedure is proposed to extract basic parameters for the AIM-Spice amorphous thin film transistor model in the above-threshold region. Our method avoids non-linear optimization, which is mainly the method utilized up to now, when using a program extractor included in AIM-Spice. The present extraction procedure is based on the integration of the experimental data current. The integration method as in known is convenient to decrease the effects of experimental noise. The method is applied to the linear and saturation regions for the above-threshold regime and allows the extraction of all the above-threshold parameters. The accuracy of the simulated curves using the parameters extracted with the new procedure is verified with measured and calculated data using the expressions contained in the model.

Exact analytical solutions of the forward non-ideal diode equation with series and shunt parasitic resistances

Abstract Exact closed form solutions based on the Lambert W -function are presented to express the forward current–voltage characteristics of non-ideal single-exponential diodes containing all possible combinations of series and shunt parasitic resistances. It is shown that these expressions could be useful for carrying out highly accurate computations at speeds almost as fast as those possible when using less precise approximate solutions based on common elementary functions.

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed

Analytic solution of the channel potential in undoped symmetric dual-gate MOSFETs

We extend our previous Lambert function-based analytic solution for the surface potential of undoped-body single-gate bulk MOSFETs to offer an explicit analytic solution of the surface potential of undoped-body symmetric dual-gate devices. The error produced by the proposed solution compared to exact results is reasonably small for typical device dimensions and bias conditions.

Exact analytical solution of channel surface potential as an explicit function of gate voltage in undoped-body MOSFETs using the Lambert W function and a threshold voltage definition therefrom

Two useful applications of the Lambert W function to undoped-body MOSFET modeling are presented. Firstly, it is applied to the problem of inverting the gate voltage versus channel surface potential equation. The result is an exact analytical solution of the channel surface potential as an explicit function of the gate voltage for either n or p channel operation. Additionally an approximate but highly accurate analytical solution is presented which is continuously valid for all regions of operation. Secondly, we propose a new unambiguous analytical definition for the threshold voltage of these undoped-body devices. This definition overcomes the impossibility of using the traditional definition based on the bulk Fermi potential, and the ambiguities introduced by other definitions. The threshold voltage is mathematically described also using the Lambert W function at the transition point from subthreshold to superthreshold behavior. An approximation for the )1 branch of the Lambert W function is proposed to express the threshold voltage approximately using elementary logarithmic functions. These new descriptions are then verified against two-dimensional numerical device simulations. 2003 Elsevier Ltd. All rights reserved.

Revisiting MOSFET threshold voltage extraction methods

Abstract This article presents an up-to-date review of the several extraction methods commonly used to determine the value of the threshold voltage of MOSFETs. It includes the different methods that extract this quantity from the drain current versus gate voltage transfer characteristics measured under linear operation conditions for crystalline and non-crystalline MOSFETs. The various methods presented for the linear region are adapted to the saturation region and tested as a function of drain voltage whenever possible. The implementation of the extraction methods is discussed and tested by applying them to real state-of-the-art devices in order to compare their performance. The validity of the different methods with respect to the presence of parasitic series resistance is also evaluated using 2-D simulations.

New method for determination of harmonic distortion in SOI FD transistors

We present a new method for calculating the total harmonic distortion (THID) and the third harmonic distortion (HD3) of the output current-voltage characteristics of a semiconductor device. The method is based on the calculation of two functions which we call D and D3 and are based on a specific integration of the DC current-voltage characteristic of the device. In this paper we demonstrate that function D can be correlated with the THD and function D3 with the HD3, so that they can be determined in a much simpler way, with no need to use derivatives, Fourier coefficients or fast Fourier transforms. The new method is applied to calculate the harmonic distortion of a silicon-on-insulator (Sol) fully depleted (FD) MOS transistor in the triode regime to be used as an active resistor at the input of an operational amplifier in a MOSFET-C filter configuration. It is also demonstrated that the transistor I-DS-V-DS characteristics used in these calculations can be obtained from either measurements, analytical models or numerical simulations

Direct extraction of semiconductor device parameters using lateral optimization method

Direct extraction of semiconductor device parameters using lateral optimization method A. Ortiz-Conde, Yuansheng Ma, J. Thomson, E. Santos, J.J. Liou*, F.J. Garco a Sa nchez, M. Lei, J. Finol, P. Layman Departamento de ElectroÂnica, Universidad SimoÂn BoloÂvar, Apartado 89000, Caracas, 1080-A, Venezuela Department of ECE, University of Central Florida, Orlando, FL 32816-2450, USA Modeling and Simulation Group, Lucent Technologies, Orlando, FL, USA Motorola, 3102 North 56th Street, Phoenix, Arizona 85018, USA