A. Chiang

Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation

The effects and kinetics of hydrogen passivation on polycrystalline-silicon thin-film transistors (poly-TFTs) are investigated. Based on the response of device parameters with the progress of hydrogenation, two types of defects can be distinguished from the difference in passivation rate. The threshold voltage and subthreshold slope, which are strongly influenced by the density of dangling bond midgap states, have a faster response to hydrogenation. The off-state leakage current and field-effect mobility, related to stain-bond tail states, respond more slowly to hydrogenation, with an onset period of approximately 4 to 12 h depending on the grain size. Since the larger-grain-size samples showed a longer onset period, the contribution of intragranular defects to the strain-bond tail states appears to be significant.<<ETX>>

Raman spectroscopy of amorphous and microcrystalline silicon films deposited by low‐pressure chemical vapor deposition

In this work we used Raman spectroscopy to investigate the structural characteristics of as‐deposited amorphous and micro‐crystalline silicon films. For amorphous silicon films, the order (or disorder) of the silicon network was quantified using properties of the Raman spectra that were related to key deposition conditions. We found that a strong relationship exists between the structural order of the silicon matrix and the deposition temperature and deposition rate. A quantitative model was proposed relating the intensity ratio of transverse optical phonon peak to longitudinal optical phonon peak to the surface diffusion length, a parameter that was calculated from available data. It was found that optimization of the as‐deposited silicon microstructure is possible by selecting deposition conditions yielding peak–ratio values in the vicinity of 0.53. For as‐deposited micro‐crystalline silicon films, Raman spectroscopy was used to estimate the initial crystalline fraction of the film and monitor the cryst...

Retardation of nucleation rate for grain size enhancement by deep silicon ion implantation of low‐pressure chemical vapor deposited amorphous silicon films

The effects of silicon ion implantation on the crystallization kinetics and grain size of low‐pressure chemical vapor deposited amorphous silicon on oxidized silicon substrate have been studied by x‐ray diffraction and transmission electron microscopy. The most effective grain size enhancement was achieved by deep silicon ion implantation with the projected range located beyond the bottom interface to allow the maximum kinetic energy transfer at or near that interface. The grain size enhancement was due to a decrease of nucleation rate and an increase of the nucleation activation barrier from 3.9 to 4.9 eV for the Si+‐implanted sample. The amorphous‐to‐crystalline grain growth activation barrier of 3.2 eV was not altered by Si+ implantation, but the growth rate was decreased. Retardation of nucleation and enhancement of grain size are attributable to the implant‐recoiled oxygen. The average grain size increases from ∼0.2 to ∼2.0 μm by using 2×1015 cm−2 of Si+ implantation at 92 keV for 82‐nm‐thick films.

Hydrogen diffusion in polycrystalline silicon thin films

Grain boundaries in undoped polycrystalline silicon (poly‐Si) thin films are shown to act as efficient hydrogen traps rather than as paths of enhanced diffusion. A comparison of hydrogen diffusion in poly‐Si and undoped single‐crystal silicon (c‐Si) demonstrates that the diffusion in poly‐Si is significantly suppressed compared to c‐Si. These results have significant implications for hydrogenation of poly‐Si thin‐film transistors.

A simpler 100-V polysilicon TFT with improved turn-on characteristics

An improved polysilicon high-voltage thin-film transistor (HVTFT) structure for eliminating the current-pinching phenomenon often observed in the conventional offset-gate polysilicon HVTFTs is discussed. The device employs, in lieu of implantation, a metal field plate overlapping the entire offset region to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current pinching effects are consistently obtained. The structure also eliminates the lightly doped drain implant required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process.<<ETX>>

Highly photosensitive transistors in single‐crystal silicon thin films on fused silica

Exceptionally high photosensitivity has been obtained in metal‐oxide‐semiconductor field‐effect transistors fabricated in single‐crystal silicon thin films on fused silica. The silicon films were laser crystallized and used to fabricate depletion mode transistors. Operating in pinch‐off these buried‐channel devices display an optical responsivity of ≳ 300 A/W of incident visible radiation. This is some four orders of magnitude greater than that achieved in enhancement mode devices of comparable design and processing. The basic mechanism for the high sensitivity is the spatial separation of photogenerated electrons and holes which results in long carrier lifetimes, as indicated by optical gains >103 and photocurrent decay times of the order of 10 μs.

Physical mechanisms for short channel effects in polysilicon thin films transistors

It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias. The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes. At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts. Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage. When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves.<<ETX>>

Mechanism and device-to-device variation of leakage current in polysilicon thin film transistors

An experimental study of mechanisms responsible for off-stage leakage currents in n- and p-channel poly-TFTs (thin-film transistors) is presented. Unlike turn-on characteristics, leakage currents are not symmetrical with respect to source-drain voltage polarity. The conduction mechanism in the off-state is consistent with the model of thermionic-field emission near the drain. The spatial and energetic distribution of trap-states in the drain depletion region affects the tunneling probability and causes device-to-device variation and the asymmetry in leakage current. The temperature dependence of the leakage current arises from the thermally activated carrier population at the energy state of the maximum tunneling probability. Cumulative leakage currents follow a Poisson-type log-normal distribution which can be significantly affected by processing control. Less than 10-fA/ mu m TFT width in leakage current and more than nine orders of magnitude on/off current ratio at 10-V drain bias were achieved in n-channel poly-TFTs.<<ETX>>

Device sensitivity of field-plated polysilicon high-voltage TFTs and their application to low-voltage operation

The device sensitivity to the offset length variations in the recently proposed field-plated (FP) polysilicon high-voltage thin-film transistor (HVTFT) has been studied. The device characteristics of the new FP-HVTFTs are found to be much more immune to misalignment errors; this is a very desirable feature, especially for large-area applications. FP-HVTFTs also exhibit lower leakage current than their conventional counterparts for up to 100-V operation. At typical low-voltage operation (e.g. 20 V), an improvement of about three orders of magnitude in the on/off current ratio can be readily achieved. These features, together with the simpler processing and improved turn-on characteristics reported earlier, make the FP-TFT a very promising device architecture for large-area microelectronics.<<ETX>>

Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs

The authors compare polysilicon n- and p-channel thin-film transistors (TFTs) which have been fabricated using either a low-temperature (<or=600 degrees C) glass compatible process or a high-temperature quartz-based technology. The former has the advantage of lower cost, while the latter offers better device performance. The significance of the differences in TFT characteristics between the two technologies is examined from the point of view of active matrix liquid crystal display design. It is shown that the low-temperature devices are adequate for implementing many of the peripheral circuits required by flat panel active matrix displays, and that simple CMOS designs remain attractive despite the relatively poor performance of the p-channel TFTs.<<ETX>>