T.Y. Huang

Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation

The effects and kinetics of hydrogen passivation on polycrystalline-silicon thin-film transistors (poly-TFTs) are investigated. Based on the response of device parameters with the progress of hydrogenation, two types of defects can be distinguished from the difference in passivation rate. The threshold voltage and subthreshold slope, which are strongly influenced by the density of dangling bond midgap states, have a faster response to hydrogenation. The off-state leakage current and field-effect mobility, related to stain-bond tail states, respond more slowly to hydrogenation, with an onset period of approximately 4 to 12 h depending on the grain size. Since the larger-grain-size samples showed a longer onset period, the contribution of intragranular defects to the strain-bond tail states appears to be significant.<<ETX>>

Retardation of nucleation rate for grain size enhancement by deep silicon ion implantation of low‐pressure chemical vapor deposited amorphous silicon films

The effects of silicon ion implantation on the crystallization kinetics and grain size of low‐pressure chemical vapor deposited amorphous silicon on oxidized silicon substrate have been studied by x‐ray diffraction and transmission electron microscopy. The most effective grain size enhancement was achieved by deep silicon ion implantation with the projected range located beyond the bottom interface to allow the maximum kinetic energy transfer at or near that interface. The grain size enhancement was due to a decrease of nucleation rate and an increase of the nucleation activation barrier from 3.9 to 4.9 eV for the Si+‐implanted sample. The amorphous‐to‐crystalline grain growth activation barrier of 3.2 eV was not altered by Si+ implantation, but the growth rate was decreased. Retardation of nucleation and enhancement of grain size are attributable to the implant‐recoiled oxygen. The average grain size increases from ∼0.2 to ∼2.0 μm by using 2×1015 cm−2 of Si+ implantation at 92 keV for 82‐nm‐thick films.

A simpler 100-V polysilicon TFT with improved turn-on characteristics

An improved polysilicon high-voltage thin-film transistor (HVTFT) structure for eliminating the current-pinching phenomenon often observed in the conventional offset-gate polysilicon HVTFTs is discussed. The device employs, in lieu of implantation, a metal field plate overlapping the entire offset region to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current pinching effects are consistently obtained. The structure also eliminates the lightly doped drain implant required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process.<<ETX>>

Physical mechanisms for short channel effects in polysilicon thin films transistors

It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias. The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes. At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts. Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage. When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves.<<ETX>>

Mechanism and device-to-device variation of leakage current in polysilicon thin film transistors

An experimental study of mechanisms responsible for off-stage leakage currents in n- and p-channel poly-TFTs (thin-film transistors) is presented. Unlike turn-on characteristics, leakage currents are not symmetrical with respect to source-drain voltage polarity. The conduction mechanism in the off-state is consistent with the model of thermionic-field emission near the drain. The spatial and energetic distribution of trap-states in the drain depletion region affects the tunneling probability and causes device-to-device variation and the asymmetry in leakage current. The temperature dependence of the leakage current arises from the thermally activated carrier population at the energy state of the maximum tunneling probability. Cumulative leakage currents follow a Poisson-type log-normal distribution which can be significantly affected by processing control. Less than 10-fA/ mu m TFT width in leakage current and more than nine orders of magnitude on/off current ratio at 10-V drain bias were achieved in n-channel poly-TFTs.<<ETX>>

Device sensitivity of field-plated polysilicon high-voltage TFTs and their application to low-voltage operation

The device sensitivity to the offset length variations in the recently proposed field-plated (FP) polysilicon high-voltage thin-film transistor (HVTFT) has been studied. The device characteristics of the new FP-HVTFTs are found to be much more immune to misalignment errors; this is a very desirable feature, especially for large-area applications. FP-HVTFTs also exhibit lower leakage current than their conventional counterparts for up to 100-V operation. At typical low-voltage operation (e.g. 20 V), an improvement of about three orders of magnitude in the on/off current ratio can be readily achieved. These features, together with the simpler processing and improved turn-on characteristics reported earlier, make the FP-TFT a very promising device architecture for large-area microelectronics.<<ETX>>

A MOS Transistor with self-aligned polysilicon source&#8212;drain

A new MOS transistor with self-aligned polysilicon source-drain (SAPSD) is demonstrated. Using a thin implant-doped polysilicon layer above the active channel region, a shallow source-drain junction with negligible leakage is realized. A novel lightly doped-drain (LDD) structure is also incorporated by diffusing dopants from the n+ polysilicon source-drain layer into the silicon substrate, forming the n- region. During the gate oxidation, a sidewall spacer is simultaneously formed by the oxidation of polysilicon source-drain sidewalls. The transistor layout area is saved by bringing the source-drain contacts onto the field oxide region. Experimental results of the new structure are presented.

Damage To Gate Oxides In Reactive Ion Etching

The damage incurred during reactive ion etching is studied by using MOS capacitors with various sizes of surface metal pads attached to the gate electrode as charge collectors. Wet oxides show a sharper breakdown distribution and a higher resistance to plasma damage than dry oxides. High resolution electron microscopy shows that the Si/Si02 interfaces of dry oxides are much rougher than that of wet oxides both in terms of the extrusion heights and spacings. An anomalous leakage current in negative-gate IV characteristics was found for fully processed CMOS transistors and capacitors with metal pad antenna, indicating the nature of electrostatic induced hole trapping near the polysilicon gate/SiO2 interface. These residual trapped charges may be due to hole tunneling from gate electrode into oxide from an induced positive-gate bias. Breakdown characteristics are significantly degraded when electrons are injected from the polysilicon gate as opposed to injection from the silicon substrate. The most prominent effect of the electrostatic damage is the degradation in breakdown voltages of the defective oxides.

Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs

The authors compare polysilicon n- and p-channel thin-film transistors (TFTs) which have been fabricated using either a low-temperature (<or=600 degrees C) glass compatible process or a high-temperature quartz-based technology. The former has the advantage of lower cost, while the latter offers better device performance. The significance of the differences in TFT characteristics between the two technologies is examined from the point of view of active matrix liquid crystal display design. It is shown that the low-temperature devices are adequate for implementing many of the peripheral circuits required by flat panel active matrix displays, and that simple CMOS designs remain attractive despite the relatively poor performance of the p-channel TFTs.<<ETX>>

Small geometry effects in n- and p-channel polysilicon thin film transistors

The authors describe the results of an experimental study of small-geometry effects in n- and p-channel polysilicon TFTs (thin film transistors) fabricated on quartz substrates. Short-channel effects are shown to be severe, with significant threshold shifts observed in devices with gate lengths of less than about 8 mu m and degradation in drain breakdown voltages for gate lengths below about 5 mu m. The performance of simple digital CMOS circuits fabricated using TFTs with a range of gate lengths is also reported, and the improvement in speed achieved by reducing gate lengths is shown. In particular, the operation of shift registers, designed using 5- mu m-long TFTs at clock frequencies in excess of 50 MHz, is demonstrated.<<ETX>>