I.-W. Wu

Retardation of nucleation rate for grain size enhancement by deep silicon ion implantation of low‐pressure chemical vapor deposited amorphous silicon films

The effects of silicon ion implantation on the crystallization kinetics and grain size of low‐pressure chemical vapor deposited amorphous silicon on oxidized silicon substrate have been studied by x‐ray diffraction and transmission electron microscopy. The most effective grain size enhancement was achieved by deep silicon ion implantation with the projected range located beyond the bottom interface to allow the maximum kinetic energy transfer at or near that interface. The grain size enhancement was due to a decrease of nucleation rate and an increase of the nucleation activation barrier from 3.9 to 4.9 eV for the Si+‐implanted sample. The amorphous‐to‐crystalline grain growth activation barrier of 3.2 eV was not altered by Si+ implantation, but the growth rate was decreased. Retardation of nucleation and enhancement of grain size are attributable to the implant‐recoiled oxygen. The average grain size increases from ∼0.2 to ∼2.0 μm by using 2×1015 cm−2 of Si+ implantation at 92 keV for 82‐nm‐thick films.

Hydrogen diffusion in polycrystalline silicon thin films

Grain boundaries in undoped polycrystalline silicon (poly‐Si) thin films are shown to act as efficient hydrogen traps rather than as paths of enhanced diffusion. A comparison of hydrogen diffusion in poly‐Si and undoped single‐crystal silicon (c‐Si) demonstrates that the diffusion in poly‐Si is significantly suppressed compared to c‐Si. These results have significant implications for hydrogenation of poly‐Si thin‐film transistors.

Optimization of BF2+ implanted and rapidly annealed junctions in silicon

The electrical properties and defect characteristics of shallow junctions fabricated by using BF2+‐ion implantation and followed by either furnace or rapid thermal annealing (RTA) have been investigated. The RTA temperature‐time cycle was optimized in terms of leakage current, junction depth, and sheet resistivity of junctions. Specifically, shallow p+ junctions (∼180 nm) with low leakage current (∼2 nA/cm2 at −5 V) were obtained with 49‐keV, 2×1015‐cm−2 BF2+ implantation and RTA at 1050 °C for 15 s. The effects of a Si+ preamorphizing implant and pre‐ or post‐RTA low‐temperature furnace anneal were also studied. p+/n diodes fabricated with a preamorphizing implantation exhibit about 3 orders of magnitude higher leakage current than the diodes without preimplantation. The excessive leakage current of the preamorphized junctions arises from a band of post‐annealing defects located in the depletion region of the n well (from ∼220 to 420 nm). Samples without the Si+ implant have very shallow and narrow defec...

Effects of backsputtering and amorphous silicon capping layer on the formation of TiSi2 in sputtered Ti films on (001)Si by rapid thermal annealing

The effects of backsputtering and amorphous silicon capping layer on the formation of TiSi2 in sputtered Ti films on (001)Si by rapid thermal annealing have been studied by scanning and transmission electron microscopy as well as Auger electron spectroscopy. Backsputtering cleaning of the silicon substrates was found to be effective in alleviating the island formation and in promoting the epitaxial growth. Auger depth profiles indicated that intermixing of Ti and Si occurred in samples with substrates cleaned by in situ backsputtering prior to depositions. High‐resolution lattice images of cross‐sectional samples revealed the presence of continuous amorphous layers between polycrystalline Ti grains and single‐crystal Si substrates in the backsputtering‐cleaned samples. An amorphous silicon capping layer was found to degrade the surface morphology and hinder the formation of silicide epitaxy. The formation and growth of epitaxial regions are more difficult in samples with amorphous silicon capping layer si...

Direct observation of crystallization in silicon by in situ high-resolution electron microscopy

Abstract We have studied the nucleation and growth of crystalline silicon by in situhigh-resolution electron microscopy. Amorphous silicon thin films, deposited onto oxidized silicon wafers by low-pressure chemical vapor deposition, were heated in the microscope in the nominal temperature range of 700–775°C. Many sub-critical crystal embryos exist at the a-Si/SiO2 interface, very few of which develop into viable nuclei. One nucleation event was recorded successfully at lattice resolution, allowing an estimate of the critical radius as 2.5±1.0 nm and the a-Si/c-Si interfacial energy as 600±200 mJ m−2. The crystal growth was followed for extended periods of time. It appeared to be characterized by sporadic growth bursts rather than a continuos advance of the crystal-amorphous phase interface. We specifically sought evidence for a ledge growth mechanism but did not find such behavior.

Physical mechanisms for short channel effects in polysilicon thin films transistors

It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias. The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes. At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts. Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage. When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves.<<ETX>>

Damage to shallow n+/p and p+/n junctions by CHF3+CO2 reactive ion etching

The damage incurred during contact etch is studied, with emphasis on determining those defects responsible for leakage current of shallow junctions. Shallow p+/n and n+/p junctions have been prepared with depths of 160–180 nm. Junction leakage and contact resistance measurements have been made for various amounts of silicon loss up to within 20 nm of the junctions during contact etch through a 300 nm of SiO2 film by using a CHF3+CO2 plasma. For p+/n junctions, the leakage current density was found to depend strongly on contact area and increase rapidly with etch depth after the etched surface has extended to within 80 nm of the junction boundary. On the other hand, the leakage current stays constant even when the etched surface approaches within 40 nm of the junction boundary for n+/p junctions. Further etching of the n+/p junction only induces punch‐through. Contact resistance was found to increase with etch depth for the p+ junctions after 50 nm of silicon was removed from the surface, and stays constan...

Mechanism and device-to-device variation of leakage current in polysilicon thin film transistors

An experimental study of mechanisms responsible for off-stage leakage currents in n- and p-channel poly-TFTs (thin-film transistors) is presented. Unlike turn-on characteristics, leakage currents are not symmetrical with respect to source-drain voltage polarity. The conduction mechanism in the off-state is consistent with the model of thermionic-field emission near the drain. The spatial and energetic distribution of trap-states in the drain depletion region affects the tunneling probability and causes device-to-device variation and the asymmetry in leakage current. The temperature dependence of the leakage current arises from the thermally activated carrier population at the energy state of the maximum tunneling probability. Cumulative leakage currents follow a Poisson-type log-normal distribution which can be significantly affected by processing control. Less than 10-fA/ mu m TFT width in leakage current and more than nine orders of magnitude on/off current ratio at 10-V drain bias were achieved in n-channel poly-TFTs.<<ETX>>

Damage To Gate Oxides In Reactive Ion Etching

The damage incurred during reactive ion etching is studied by using MOS capacitors with various sizes of surface metal pads attached to the gate electrode as charge collectors. Wet oxides show a sharper breakdown distribution and a higher resistance to plasma damage than dry oxides. High resolution electron microscopy shows that the Si/Si02 interfaces of dry oxides are much rougher than that of wet oxides both in terms of the extrusion heights and spacings. An anomalous leakage current in negative-gate IV characteristics was found for fully processed CMOS transistors and capacitors with metal pad antenna, indicating the nature of electrostatic induced hole trapping near the polysilicon gate/SiO2 interface. These residual trapped charges may be due to hole tunneling from gate electrode into oxide from an induced positive-gate bias. Breakdown characteristics are significantly degraded when electrons are injected from the polysilicon gate as opposed to injection from the silicon substrate. The most prominent effect of the electrostatic damage is the degradation in breakdown voltages of the defective oxides.

Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs

The authors compare polysilicon n- and p-channel thin-film transistors (TFTs) which have been fabricated using either a low-temperature (<or=600 degrees C) glass compatible process or a high-temperature quartz-based technology. The former has the advantage of lower cost, while the latter offers better device performance. The significance of the differences in TFT characteristics between the two technologies is examined from the point of view of active matrix liquid crystal display design. It is shown that the low-temperature devices are adequate for implementing many of the peripheral circuits required by flat panel active matrix displays, and that simple CMOS designs remain attractive despite the relatively poor performance of the p-channel TFTs.<<ETX>>