A. Concannon

Two-dimensional numerical analysis of floating-gate EEPROM devices

The importance of transient analysis in the design of floating-gate EEPROMs is demonstrated. Anomalous behavior, which was identified during transient measurements, has been simulated using HFIELDS, a general-purpose two-dimensional (2D) numerical device simulator. The corrective action that was taken at the time to eliminate the problem has been analyzed and explained using the simulation results. In addition, the simulator has been used to investigate 2D effects in the device due to process nonidealities. >

Modeling and simulation of reliability for design

Abstract This paper provides a review of the use of simulation tools in the design process. It provides examples of applications where such tools can be effective in improving device functionality, yield, manufacturability and reliability. Topics covered are numerical process and device simulation, electromigration and stress migration simulation as well as circuit simulation and reliability modelling. Specific example of how such simulators work are provided and examples of currently available software tools are reviewed.

Bistable gated bipolar device

We report a semiconductor device that exhibits a negative differential resistance characteristic. The device has the same structure as metal-oxide-semiconductor (MOS) transistors currently used in integrated circuits. Biasing the structure in the subthreshold regime and sweeping the bulk bias results in the negative differential resistance characteristic. The device exhibits a peak valley current ratio of approximately 52 at room temperature while drawing ten nanoampers of current which is of sufficiently low power for ultra-large scale integration (ULSI) applications.

Extraction of coupling ratios for Fowler–Nordheim programming conditions

Abstract An analysis of extraction methodologies for the coupling ratios in non-volatile memories using numerical simulation is presented. The floating gate voltage of a non-volatile memory (NVM) cell cannot be accessed directly from measurements but can be derived using numerical simulation techniques. In this paper, various coupling ratio methodologies from literature are investigated using numerical simulation techniques and guidelines on improving the application of these methods to NVM cells are outlined. Measurements are performed which validate the increased accuracy of the methods and some of the improved methodologies are recommended for coupling ratio extraction in the Fowler–Nordheim regime. This work demonstrates the role of numerical simulation in supplementing the electrical characterisation of NVM cells.

The numerical simulation of substrate and gate currents in MOS and EPROMs

The gate current that flows during programming in the flash EEPROM device is a result of hot electron injection from the channel. The channel doping is high and the drain junction is abrupt and optimised to enhance the hot carrier avalanche generation in the silicon near the drain junction. As in the case with conventional MOS, this has the further impact of creating a high substrate current. In this work, a new model for both substrate and gate current using the same hot carrier energy distribution function in both models is presented. These models predict gate and substrate currents over a wide range of gate voltages and have been validated for both electron and hole hot carrier avalanche generation in n- and p-channel transistors. These models have been used to simulate flash EEPROM programming so that reliability issues, particularly with respect to the effect of the gate current due to hot hole injection, could be investigated.

Analysis of external latch-up protection test structure design using numerical simulation

With each new CMOS technology the latch-up sensitivity and eAects of prevention strategies change. Products built in these technologies must adhere to stringent guidelines for latch-up ‘Hardness’, and for this reason characterisation of new technologies is needed through the use of test structures. This paper shows a numerical simulation approach which can determine the relative eAectiveness of guard-rings in ESD protection device test structures. In this work, time taken to characterise latch-up protection test structures and to chose a protection strategy is greatly reduced by using numerical simulations to design the test structures. The results presented are for variations to the guard-rings for two technologies. Included in these are the typical simulation times and resources required. The technique outlined has the joint advantages of providing accurately representative simulations of the technology and test structure layout in a practical time frame. # 1999 Elsevier Science Ltd. All rights reserved.

A novel CMOS-compatible top-floating-gate EEPROM cell for embedded applications

A novel nonvolatile memory top-floating-gate (TFG) device is demonstrated in a CMOS technology. This device differs in both structure and operation to typical split-gate or stacked-gate approaches. The TFG device offers low development cost, low power compliance, and high reliability. It can be fabricated using routine CMOS processing making it clearly competitive to options typically used in the industry. The structure and operation of this novel device structure is described. This is followed by a description of the processing steps required and measured electrical results.

Theoretical Analysis of a Pseudo-Floating Gate flash EEPROM Device

In this paper the program, erase and read operations of a novel non›volatile memory transistor are investigated using numerical device simulation. The physical mechanisms that enable this device to operate as a non›volatile memory are analysed. This approach is demonstrated to be a promising concept, suitable for low power CMOS embedded memory.

Compact model development for a new non-volatile memory cell architecture

An accurate SPICE compatible model for a novel flash memory device, the Top Floating Gate (TFG) cell, is described. This device can be integrated into CMOS processes with minimal disruption to the standard process. The cell is programmed and erased by Fowler Nordheim tunnelling, which is a low power operation thereby complying with a major requirement of system-on-chip applications. The development of an accurate model for flash memory is complicated by the variable nature of the cell. In standard flash memory, the threshold voltage and, therefore, the drain current of the cell vary as the cell is programmed or erased. In the TFG case, both the threshold voltage and series resistance vary which further complicates the model development. Our model has been found to be accurate over the full range of floating gate charge.

Extraction of the coupling coefficients for the top-floating-gate (TFG) flash EEPROM cell

A novel measurement technique utilising a new test structure is applied to the existing subthreshold methodology to extract coupling coefficients of the Top-Floating-Gate (TFG) cell. The TFG cell is unique in structure and operation in comparison with current NVM devices. It is designed with the FG surrounding the CG which greatly enhances the gate coupling ratio (/spl alpha//sub cg/) allowing a small area cell and avoiding the use of expensive z-direction extensions unlike the industry standard stacked-gate approach. This work quantifies this benefit for the area efficient TFG cell design.