Russell Duane

Characterization of micromechanical structures using white-light interferometry

As microelectromechanical systems (MEMS) move rapidly towards commercialization, the issue of mechanical characterization has emerged as a major consideration in device design and fabrication. It is now common to include a set of test structures on a MEMS wafer for extraction of thin film material properties (in particular, residual stress, stress gradient and Youngs modulus), and for process and device monitoring. These structures usually consist of micromachined beams and strain gauges. Measurement techniques include tensile testing, scanning electron microscopy (SEM) imaging, atomic force microscopy (AFM) analysis, surface profiling and Raman spectroscopy. However, these tests are often destructive and may be difficult to carry out at the wafer scale. Instead of these methods, this paper uses white-light interferometry surface profiling for material characterization and device inspection. Interferometry is quick, non-destructive, non-contact, and can offer a high density lateral resolution with extremely high sensitivities to the surface in the z-direction—all essential requirements for high volume manufacturing. A range of devices is employed to illustrate the capabilities of white-light interferometry as a measurement and process characterization tool.It is shown that residual stress may be determined by using electrostatic actuation to pull fixed–fixed beams towards the substrate, and interferometry to record the beam deflection profile. Finite-element simulation software is employed to model this deflection, and to estimate the material properties which minimize the difference between the measured and simulated profiles. The results agree well with blanket film measurements.

Analysis of electromechanical boundary effects on the pull-in of micromachined fixed-fixed beams

Using a commercial finite-element simulation tool, this work considers some of the electromechanical effects commonly neglected during the analysis of electrostatically actuated fixed–fixed beams. These structures are used in many applications of micromechanical systems, from relay switches and RF resonators to thin film characterization tests, but much of the analytical modelling of the device behaviour disregards the effects of electrostatic field fringing, plane-strain conditions and anchor compliance. It is shown that the cumulative total of these errors can be substantial, and may lead to large discrepancies in the expected operational characteristics of the device. We quantify the influence of these effects on the electrostatic pull-in of fixed–fixed beams, and illustrate some of the limitations of ideal pull-in theory. In order to more accurately predict the pull-in voltage for a real structure, a model is developed that combines ideal case theory with anchor compliance correction factors extracted using finite-element analysis. Three common anchor types (ideal, step-up and cup-style) are characterized. The final model takes account of the compliance of the beam anchors, electrostatic field fringing and plane-strain effects, and agrees well with simulated results.

Radiochemistry on chip

We have developed an integrated microfluidic platform for producing 2-[(18)F]-fluoro-2-deoxy-D-glucose ((18)F-FDG) in continuous flow from a single bolus of radioactive isotope solution, with constant product yields achieved throughout the operation that were comparable to those reported for commercially available vessel-based synthesisers (40-80%). The system would allow researchers to obtain radiopharmaceuticals in a dose-on-demand setting within a few minutes. The flexible architecture of the platform, based on a modular design, can potentially be applied to the synthesis of other radiotracers that require a two-step synthetic approach, and may be adaptable to more complex synthetic routes by implementing additional modules. It can therefore be employed for standard synthesis protocols as well as for research and development of new radiopharmaceuticals.

Performance and reliability of post-CMOS metal/oxide MEMS for RF application

This paper describes work carried out to assess the elastic performance of microelectromechanical (MEMS) test structures in a post-CMOS (complementary metal oxide semiconductor) metal oxide process. Electrostatic pull-in measurements are used to extract the residual stress, elastic modulus and stress-gradient for the process. Results are presented for metal structures and for composite metal/oxide structures. The extracted parameters are compared with values obtained from blanket film measurements and from analysis based on bulk material properties. Test structures have also been tested for cycling repeatability. A drift is observed in successive cycles of electrostatic actuation and this drift is attributed to charge trapping in the nitride passivation of the underlying CMOS process. A charge-balance model is used to estimate the trapped charge and the effect of actuation voltage polarity is also discussed. The results indicate that satisfactory elastic performance of mechanical structures is dependent on process conditions but can be achieved. The stability of electrical operating characteristics is dominated by nitride charge trapping effects. This effect can be quantified using a basic model. To minimize problems due to charge trapping dielectric properties must be investigated and operating characteristics modified.

LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide

We investigate planar fully depleted silicon-on-insulator(SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at Vdd = 1 V. The shift of the threshold voltage ΔVth with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported.

Modeling and simulation of reliability for design

Abstract This paper provides a review of the use of simulation tools in the design process. It provides examples of applications where such tools can be effective in improving device functionality, yield, manufacturability and reliability. Topics covered are numerical process and device simulation, electromigration and stress migration simulation as well as circuit simulation and reliability modelling. Specific example of how such simulators work are provided and examples of currently available software tools are reviewed.

A simple electrical test method to isolate viscoelasticity and creep in capacitive microelectromechanical switches

A bipolar hold-down voltage was used to study mechanical degradation in radio-frequency microelectromechanical capacitive shunt switches. The bipolar signal was used to prevent the occurrence of dielectric charging and to isolate mechanical effects. The characteristics of material stress relaxation and recovery were monitored by recording the change of the pull-in voltage of a device. The creep effect in movable components was saturated by repeated actuation to the pulled-in position, while comparison with a theoretical model confirmed the presence of linear viscoelasticity in the devices.

Bistable gated bipolar device

We report a semiconductor device that exhibits a negative differential resistance characteristic. The device has the same structure as metal-oxide-semiconductor (MOS) transistors currently used in integrated circuits. Biasing the structure in the subthreshold regime and sweeping the bulk bias results in the negative differential resistance characteristic. The device exhibits a peak valley current ratio of approximately 52 at room temperature while drawing ten nanoampers of current which is of sufficiently low power for ultra-large scale integration (ULSI) applications.

Design for reliability

Abstract The advent of the ULSI era, and the continuing decrease of the critical dimensions of MOSFETs, has raised a number of issues concerning the prediction of device reliability, and the consequences for overall product reliability. The established practice has been to assure reliability at the end of the lengthy product cycle. However, to achieve a shorter time-to-market, product reliability concerns should be addressed at the design stage (“design for reliability”). Accordingly, the design and implementation of reliability simulation tools, which give a prediction of the susceptibility of an IC design to device failure mechanisms, is becoming critical. This paper reviews some of the reliability simulation tools that are currently available to industry. The capability of the most popular of these tools is described for a number of different reliability hazards. A topical reliability simulation issue is addressed, and a statistical validation, comparing measured and simulated degraded ring oscillator data, is presented.

LDD depletion effects in thin-BOX FDSOI devices with a ground plane

In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.