J.D. van der Tang

Explicit design equations for class-E power amplifiers with small DC-feed inductance

This paper presents novel, explicit design equations for class-E power amplifiers with finite DC-feed inductance. A mathematically exact analysis of the idealized class-E power amplifier with small DC-feed inductance shows that the circuit element values are transcendent functions of the input parameters. Therefore, the designer needs to perform a long iterative procedure in order to find these values. We have solved the circuit operation for a certain number of cases, and performed a Lagrange polynomial interpolation in order to obtain explicit, directly usable design equations. The proposed design method is verified by simulation and the agreement with the theory is excellent.

A high gain, low voltage folded-switching mixer with current-reuse in 0.18 /spl mu/m CMOS

The scaling of CMOS technologies has a great impact on analog design. The most severe consequence is a reduction of the voltage supply. In this article, a new low voltage folded-switching mixer with current reuse, which operates at 1 V supply voltage, is discussed. The main advantages of the introduced mixer topology are: a high voltage gain, a moderate noise figure and an operation at low supply voltages. Full insight into mixer operation is given by analyzing voltage gain, noise figure, linearity (IIP3) and DC stability. The mixer is designed and implemented in 0.18 /spl mu/m CMOS technology with MIM capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz, a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of 3.2 mW.

A FSK demodulator comparison for ultra-low power, low data-rate wireless links in ISM bands

Personal communications require wireless nodes, which can transmit and receive reliably data under huge power constraints. Higher level of integration and reduction of power consumption can be achieved using a zero-IF architecture together with a wideband BFSK modulation scheme. Unfortunately FSK techniques performances degrade sharply in the presence of frequency offset. In this paper a comparison between potentially low power BFSK architectures is presented based on high level models. In depth analysis of four potentially low power demodulators shows that the architecture, which can assure rejection of large static offset with minimum increment in hardware complexity is the ST-DFT based demodulator. This will allow great reduction in power consumption avoiding acquisition and tracking of the offset at the receiver side.

On the feasibility of application of class E RF power amplifiers in UMTS

This paper investigates the feasibility of the application of class E RF power amplifiers in UMTS. A typical class E circuit has been designed and simulated, in conjunction with a linearization scheme based on the EER principle. The EER testbench uses ideal building blocks, since the emphasis is on the operation of the amplifier itself. Three different technologies have been used for the active device (Si BJT, GaAs HBT and CMOS) in order to examine the influence of the device technology on the PA performance. Relevant parameters have been monitored and put in the table form, for comparison of technologies. The simulation results indicate that class E PAs can successfully be used for power amplification of WCDMA RF signal and that GaAs technology is offering the highest efficiency.

Adaptive multi-standard RF front-ends

Glossary. Abbreviations. 1 Introduction. 1.1 The state-of-the-art in multi-standard RF transceivers. 1.2 Scope. 1.3 Outline. 2 Front-end architecture selection. 2.1 A generic front-end architecture. 2.2 A set of front-end architectures. 2.3 Selection criteria. 2.4 Selection of a suitable front-end architecture. 2.5 Summary. 3 Broad-band polyphase filters. 3.1 Passive polyphase filter topology. 3.2 RC polyphase filters and their applications. 3.3 Design considerations. 3.4 Summary. 4 Analysis of low-IF architectures. 4.1 Noise and voltage gain analysis in a low-IF front-end. 4.2 Linearity analysis. 4.3 Image rejection analysis. 4.4 Summary. 5 RF and building block specifications. 5.1 RF specifications. 5.2 Distribution of building block specifications. 5.3 Summary. 6 A low-voltage folded switching mixer. 6.1 Transconductors for folded switching mixers. 6.2 AC-coupled folded switching mixer with current-reuse. 6.3 Simulation and experimental results. 6.4 Mixer benchmarking. 6.5 Summary. 7 Multi-band reconfigurable complex mixer. 7.1 1.9 - 2.4 GHz reconfigurable complex mixer. 7.2 1.9 - 2.4 GHz conventional complex mixer. 7.3 Summary. 8 Reconfigurable multi-band LNA. 8.1 Design considerations. 8.2 Design procedure. 8.3 Design example. 8.4 A reconfigurable multi-band DECT/Bluetooth LNA. 8.5 Summary. 9 Reconfigurable multi-band RF front-end. 10 Conclusions. A RF, system and bulding block specifications. B Noise factor of a two-port network. C Noise factor of a passive RF block. References.

Mixer topology selection for a 1.8 - 2.5 GHz multi-standard front-end in 0.18 /spl mu/m CMOS

In this paper the selection of a mixer topology for a multi-standard, non-concurrent front-end is presented. The front-end is designed for Digital Enhanced Cordless Telephone (DECT) systems and systems for wireless communications, which operate in the 2.4 GHz Industrial Scientific Medical (ISM) band (like Bluetooth or DECT alike systems at 2.4 GHz). Three mixer topologies are presented and evaluated. In order to choose the most promising one, a figure of merit for mixers is defined. A novel, folded switching mixer topology utilizing a current reuse technique achieves the best performance. With this topology the following simulation results are achieved: noise figure (NF) 11 dB, voltage gain 17 dB, linearity (IIP/sub 3/) 1 dBm with a power consumption of 5 mW at an operating frequency of 2.5 GHz. Given the fast migration of the CMOS technologies towards the deep submicron processes, mixer operation at low supply voltages is considered. The operation at a supply voltage of 1 V providing moderate NF, gain and linearity for two mixer topologies is shown, which is not reported in the literature so far.

A surface-mounted RF IC technology demonstrated with a 10 GHz LC oscillator with copper coils

A surface-mounted RF IC fabrication technology is presented that includes a substrate transfer processing step to glass. The fabrication technology uses copper in one of the last fabrication steps to form contacts and inductors. To demonstrate the technology, a differential varactorless 10 GHz LC oscillator is fabricated. The quality factor of the used 0.63 nH inductor is estimated by measuring the required start-up current of the oscillator. With a supply voltage of 3 V, the estimated quality factor is as high as 39 at 10 GHz. At 10 GHz the dissipation of the oscillator core is 0.42 mW (with 3 V supply voltage) and the measured phase noise better than -94.7 dBc/Hz at 1 MHz offset of the carrier. By increasing the bias current, the frequency can be tuned from 10.2 GHz to 8.7 GHz, which corresponds to a 15.8% tuning range. The proposed fabrication technology eliminates bond-wires, reduces cross-talk and yields excellent passives.

A 5.3 GHz phase shift tuned I/Q LC oscillator with 1.1 GHz tuning range

In this paper phase shift tuning of a 5.3 GHz quadrature LC oscillator is investigated. By varying the phase shift of the circuits that couple two LC oscillator stages, a 1.1 GHz tuning range is achieved. Dependency of tuning range and phase noise on the quality factor of the LC resonators is explored on the behavioral level. Expressions are given for the tuning range and an effective quality factor, as a function of the resonator quality, its phase shift and its resonance frequency. The oscillator is realized in a mainstream 30 GHz f/sub T/ BiCMOS process and dissipates 45 mW (nominal) with 2.7 V supply voltage. The dependency of the tuning range on the resonator quality is measured by varying the quality factor of a varactor incorporated in the LC resonators of the I/Q oscillator. Measured /spl Lscr/(2 MHz) is -108 dBc/Hz at 5.6 GHz.In this paper phase shift tuning of a 5.3 GHz quadrature LC oscillator is investigated. By varying the phase shift of the circuits that couple two LC oscillator stages, a 1.1 GHz: tuning range is achieved. Dependency of tuning range and phase noise on the quality factor of the LC resonators is explored on the behavioral level. Expressions are given for the tuning range and an effective quality factor, as a function of the resonator quality, its phase shift and its resonance frequency. The oscillator is realized in a mainstream 30 GHz f/sub T/ BiCMOS process and dissipates 45 mW (nominal) with 2.7 V supply voltage. The dependency of the tuning range on the resonator quality is measured by varying the quality factor of a varactor incorporated in the LC resonators of the I/Q oscillator. Measured /spl Lscr/(2 MHz) is -108 dBc/Hz at 5.6 GHz.