A. Higashisaka

Light emission and burnout characteristics of GaAs power MESFET's

In order to obtain information on the field distributions and weak places of GaAs power MESFETs, the light emission and pulse burnout characteristics were investigated. Their dependence on the drain structure was also studied. The light emission occurs at the drain edge of the active region when the gate bias is zero volt, slightly changing its place depending on the drain structure. The drain edge of the epitaxial layer was also damaged by the pulse burnout experiments at zero gate bias. When the gate bias is increased, the light emission at the drain edge decreases rapidly until the gate Schottky breaks down and begins to give the light emission at the gate edge. The pulse burnout experiments suggest that the burnout initiates inside of the active or buffer epitaxial layer when the gate bias is near the pinchoff voltage.

A high-power GaAs MESFET with an experimentally optimized pattern

A high-power GaAs MESFET with a high packing density has been developed in order to increase the total gatewidth within limited practical device size. The gate-finger width was experimentally optimized to increase the packing density without deterioration of the power gain. The developed power MESFET is the crossover structure and has a total gatewidth of 15 mm with gate-finger width of 190 µm in a 2.2-mm-wide chip. The packing density was almost doubled, and the output powers of 25 W at 6 GHz, and 17 W at 8 GHz were obtained from the internally matched four-chip devices.

Broad-Band Internal Matching of Microwave Power GaAs MESFET's

Broad-band internal matching techniques for high-power GaAS MESFETs at C band have been developed adopting novel circuit configurations and large-signal characterizations in the circuit design. The lumped-element two-section input matching network is formed on a single ceramic plate with a high dielectric constant. The semidistributed single-section output circuit is formed in microstrip pattern on an alumina plate. The internally matched GaAs FET with 11200-mu m total gate width developed has a 2.5-W power output at 1-dB gain compression and a 4.4-W saturated power output with 5.5-dB linear gain from 4.2 to 7.2 GHz without external matching. The FET internally matched from 4.5 to 6.5 GHz exhibited 5-W saturated power output with 6-dB linear gain.

A high-power microwave GaAs FET oscillator

An integrated circuit GaAs FET with an oscillator power output of 220 mW and a power-added efficiency of 21% obtained at 6 GHz, will be discussed.

A stabilized, low-noise GaAs FET integrated oscillator with a dielectric resonator at C-band

TO USE G a h FET oscillators as power source in microwave communication systems, good temperature frequency-stability and low noise characteristic are essential’. A GaAs FET integrated oscillator stabilized with a high-Q dielectric resonator has been found to provide a highly-frequencystabilized, low-noise, compact RF power source. To realize optimal coupling between the oscillator and stabilizing resonant circuits, a large-signal design study was undertaken involving the measurement of the dynamic properties of the oscillator and resonant circuit. A stabilized oscillator output of 1OOmW with 17% efficiency and frequency temperature coefficient as low as 2.3 ppm/OC was obtained at 6-HGz. The FM noise characteristic has been improved more than 30dB by introducing the dielectric resonator. A common-source GaAs FET oscillator affords improved microwave performance through the optimization of the external feedback network. An unstabilized oscillator, with a series connection of microstrip lines and a dielectric capacitor as a feedback network2 generates 400-mW of microwave power with 38% efficiency at 6000MHq which is comparable to the maximum added power for an amplifier using an FET chip obtained from the same wafer.

A CML compatible GaAs gate array

This paper will describe a CML compatible GaAs 3K array using buffered FET logic. Propagation delays of 59ps and 186ps per gate were achieved for load conditions of 65μm and 2mm line lengths, respectively. 32b shift register operation at 1.2 GHz clock rates was verified.

A GaAs 12 × 12 bit expandable parallel multiplier LSI using sidewall-assisted closely-spaced electrode technology

A high speed GaAs 12 × 12 bit expandable parallel multiplier LSI has been designed and fabricated, which can perform within a 4.0 ns critical path delay. The LSI is implemented in depletion mode FET logic gates (BFL and SCFL), because of their high load drivability and large noise margin. Booths algorithm and Wallaces tree scheme were used for generating partial products and for adding them, respectively. In order to obtain high speed logic operation, the sidewall-assisted closely-spaced electrode technology (SACSET) was developed and successfully applied to the LSI fabrication.

Depletion-type GaAs MSI 32b adder

A GaAs MSI 32b adder, using depletion-type 8FL gates, will be described. The circuit uses 420 gates (2100 FETs and 420 diodes) within an area of 4.6mm×2.5mm. A 3ns carry propagation delay was obtained with 340mW total power dissipation.

X-and Ku-Band Performance of Submicron Gate GaAs Power FET's

A submicron gate technology has been applied to the development of large source periphery X-band power FETs. The developed devices delivered 1.0 W saturated output power at 11 GHz with a linear gain of 5.5 dB and a power added efficiency of 18.5%. At 13.6 GHz, a saturated power of 0.63 W was obtained with a linear gain of 4.5 dB. The developed devices have a cross over structure with interdigitated gate fingers. The basic pattern of the device was designed by calculating the gate-source transmission line loss at the gate fingers and the thermal resistance as a function of the spacing between each active region.

A CML GaAs 4Kb SRAM

A CML GaAs 1k-word by 4b SRAM for high-speed computer cache memory, exhibiting 2.4ns address access time with 1.1W power dissipation will be reported.