Takashi Furutsuka

Improvement of the drain breakdown voltage of GaAs power MESFET's by a simple recess structure

Dependence of the drain-to-source breakdown voltage on the drain structure of GaAs power FETs was investigated. It was found that the drain breakdown voltage is improved by a simple recess structure without surface n+contact layer. This is due to relaxation of the field at the drain region by increase of the thickness of the active epitaxial layer. The GaAs MESFET with this simple recess structure could be operated up to 24 V. There was no explicit difference in the microwave properties of both recess structure devices with and without the n+contact layer. As a practical device, an output power of more than 3 W with 4-dB gain is obtained at 6.5 GHz from this simple recess and cross-over structure GaAs FET.

GaAs dual-gate MESFET's

Performance of GaAs dual-gate MESFET, including high-frequency noise behavior, was analyzed on the basis of Statzs model. Under the design considerations developed from the analysis, fabrication and characterization of a prototype device were carried out. The present analysis was confirmed to reproduce satisfactorily the performance observed. Minimum noise figure and associated gain observed in the device with two 1-µm gates were; 1.2 dB and 16.7 dB at 4 GHz, 2.2 dB and 16.3 dB at 8 GHz, and 3.2 dB and 12.6 dB at 12 GHz, respectively. More than 35-dB gain controllability was also obtained at 8 GHz.

A high transconductance GaAs MESFET with reduced short channel effect characteristics

A high gm, 375 mS/mm (Vth= -0.09 V), has been achieved from a 0.3 µm long gate GaAs MESFET with a very small short channel effect by employing an MBE grown channel layer. The maximum K - value obtained was 410 mS/Vmm, which is the highest ever reported for GaAs MESFETs. A unique technology, combining sidewall - assisted self - alignment technology (SWAT) and refractory metal gate n+selective ion - implantation technology, was successfully applied to the fabrication of a GaAs MESFET with MBE grown channel layer in this work, resulting in a very low source series resistance of 0.3 Ωmm. FET characteristic dependences on gate length were also compared for FETs with different doping concentrations. The highly doped channel turned out to be effective to reduce the short channel effects and to improve the FET load drivability.

A CML compatible GaAs gate array

This paper will describe a CML compatible GaAs 3K array using buffered FET logic. Propagation delays of 59ps and 186ps per gate were achieved for load conditions of 65μm and 2mm line lengths, respectively. 32b shift register operation at 1.2 GHz clock rates was verified.

A High Performance LDD GaAs MESFET with a Refractory Metal Gate

I . INTRODUCTION In order to achieve ultrahigh-speed pedormance in GaAs LSIs, it is quite important to make a further improvement in the load drivability of the basic togic gates and, hence, to increase the transconductance (g-) of GaAs MESFETs. To this end, many MESFET technologies have been developed demonstrating their potentialities, such as SAINTI), refractory metal gate n* self-alignment technology2), Pt buried gate layer technologyS), and closely-spaced electrode technology4).

A GaAs 12 × 12 bit expandable parallel multiplier LSI using sidewall-assisted closely-spaced electrode technology

A high speed GaAs 12 × 12 bit expandable parallel multiplier LSI has been designed and fabricated, which can perform within a 4.0 ns critical path delay. The LSI is implemented in depletion mode FET logic gates (BFL and SCFL), because of their high load drivability and large noise margin. Booths algorithm and Wallaces tree scheme were used for generating partial products and for adding them, respectively. In order to obtain high speed logic operation, the sidewall-assisted closely-spaced electrode technology (SACSET) was developed and successfully applied to the LSI fabrication.

A CML GaAs 4Kb SRAM

A CML GaAs 1k-word by 4b SRAM for high-speed computer cache memory, exhibiting 2.4ns address access time with 1.1W power dissipation will be reported.

GaAs power MEWFETs with a simplified recess structure

A simplified recess structure to reduce the drain breakdown voltage of GaAs power FETs will be covered. The structure, with an internal matching network has delivered an output power of 7W at 5.6GHz.

A GaAs buffering circuit LSI for ultra-fast data processing systems

A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 mu m. WSi-W bilayer metallization system was used to reduce the gate resistance.<<ETX>>