A.J. Bhavnagarwala

Dynamic-threshold CMOS SRAM cells for fast, portable applications

A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER and lowers cell standby power by over an order of magnitude is proposed. These improvements are achieved by implementing a scheme of WL transition triggered pulses on source and substrate terminals of cell inverter transistors that share a common WL.

The impact of stochastic dopant and interconnect distributions on gigascale integration

Opportunities for GSI are governed by a hierarchy of physical limits whose five levels can be codified as: fundamental, material, device, circuit, and system. This distinctive methodology is extended here by elucidating the impact on GSI of random dopant atom placement in the channel region of a MOSFET and of interconnect distributions in random logic networks in context with projected advances in device and circuit techniques.

Circuit techniques for low-power CMOS GSI

For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60/spl deg/K above room temperature.

Minimum supply voltage for bulk Si CMOS GSI

Limits on energy dissipation are investigated for bulk Si CMOS circuits at each node of the 1997 National Technology Roadmap for Semiconductors (NTRS). Physical, continuous and smooth MOSFET transregional drain current models that consider high-field effects in scaled devices, and permit trade-offs between saturation drive current and subthreshold leakage current are described and employed to model CMOS circuit performance and power dissipation at low voltages. The transregional models are used in conjunction with physical threshold voltage roll-off models and stochastic interconnect distributions, at performances, chip sizes and transistor counts forecast by the 1997 NTRS, to project optimal supply and threshold voltages, minimizing total energy dissipated by CMOS logic circuits. Techniques exploiting datapath parallelism to further reduce-supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling.

Generic models for interconnect delay across arbitrary wire-tree networks

New, generic and compact closed-form expressions for distributed wire-tree delay dependence on input ramp time, tree topology and wire geometries are reported. In agreement to within 5% of HSPICE simulations, these expressions permit rapid, accurate and early estimates of interconnect delay as well as variations in interconnect delay due to variations in interconnect process parameters across arbitrary distributed wire-tree networks.

CMOS system-on-a-chip voltage scaling beyond 50nm

The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected local and global clock rates for high performance processors. Physical short-channel MOSFET models that consider high-field effects, threshold voltage roll-off and reverse subthreshold swing roll-off are employed in tandem with stochastic interconnect distributions to calculate optimal supply voltage, threshold voltage and gate sizes that minimize total CMOS power dissipation by exploiting trade-offs between saturation drive current and subthreshold leakage current and between device size and wiring capacitance. CMOS power dissipation at its lower limit, increases exponentially with clock frequency imposing limits on performance set by heat removal. Heat removal constraints at high local clock rates, limiting the average wire length and device size within a local zone of synchrony, or macrocell, in a short-wire cellular array architecture are used to project the maximum macrocell size and count for generations beyond 100nm.

Fluctuation Limits on Scaling of CMOS SRAMs

Reductions in CMOS SRAM cell static noise margin (SNM) due to intrinsic threshold voltage fluctuations in uniformly doped minimum geometry cell transistors are reported. Standard deviations in SNM due to random dopant placement alone are projected to exceed 17% of the nominal SNM for CMOS generations beyond 100nm posing severe barriers to scaling of supply voltage and channel length in SRAM dominated CMOS ASICs and microprocessors.

Optimal circuit design for low power CMOS GSI

For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60/spl deg/K above room temperature.

Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010

Circuit design techniques minimizing total power drain of a static CMOS gate for a prescribed performance and an operating range of temperatures are employed to project supply voltages, power densities, device threshold voltages and critical path device channel widths for CMOS ASIC technology generations listed in the 1994 NTRS (National Technology Roadmap for Semiconductors) up to the year 2010. These projections are consistent with 1994 NTRS technology and cycle time forecasts and use physical and stochastic models that tightly couple together the device, circuit and system levels of the CMOS ASIC design hierarchy. Verified by HSPICE and actual microprocessor implementations, these models project optimal supply voltages for 0.25-0.07 /spl mu/m generations to scale from 900 mV to 500 mV and power densities to increase from 3 W/cm/sup 2/ to 10 W/cm/sup 2/ in wire limited high performance CMOS ASIC systems.

Impact of interconnect parameter variations on wire-tree delay

Abstract New distributed wire-tree and stochastic delay distribution models are proposed to assess the impact of interconnect process parameter variations on fluctuations in interconnect delay. Closed-form expressions for distributed wire-tree delay reported are accurate to within 5% of HSPICE simulations. These are used in tandem with stochastic models for delay distributions to estimate deviations in interconnect delay. Deviations in interconnect delay are reported to increase as the square of interconnect length and inversely with interconnect width. Introduction With scaling of minimum feature size, although interconnect delay increases can be limited to 30% per generation by reverse scaling of metal and insulator dimensions [1], interconnect delay and variations in interconnect delay increasingly limit chip speed and delay variation margins [2,3,4]. While interconnect delay imposes constraints on maximum interconnect length, variations in interconnect delay that increase sharply at smaller line widths [5] also impose constraints on minimum interconnect width along RC limited paths. Accurately estimating interconnect delays and variations in interconnect delay along arbitrary wire tree networks, due to interconnect parameter variations is thus essential to optimizing wire geometries and repeater circuitry along RC limited paths. First-order path-tracing RC tree methods [6] based on the Elmore delay model [7] lack in accuracy in estimating delays across distributed wire-tree networks. The Q order and more accurate Asymptotic Waveform Evaluation (AWE) extensions [8,9] require formulating and solving nodal matrices where computational effort and memory requirements increase with chip and wire-tree complexity even though these techniques are more efficient than realtime HSPICE simulations. Recent attempts to estimate the impact of interconnect process variations on clock skew and interconnect delay [3] employ Monte Carlo simulations using a finite-difference solver. Any of the above methodologies to estimate wire-tree delay and/or variations in wire-tree delay would incur increasing costs in accuracy or in computational time and effort with increase in chip and interconnect complexity. Sakurai’s accurate (<3% error) closed-form analytical models for distributed interconnect delay [10] that apply only to the case of step excitations at the input of a buffer driving a 2-pin net are extended in this work to the more commonly encountered and complex cases