Blanca L. Austin

A physical alpha-power law MOSFET model

A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original Alpha-Power Law Model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: (1) a subthreshold region of operation for evaluating the on/off current trade-off that becomes a dominant low power design issue as technology scales, (2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and (3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to NTRS extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration (GSI).

The impact of stochastic dopant and interconnect distributions on gigascale integration

Opportunities for GSI are governed by a hierarchy of physical limits whose five levels can be codified as: fundamental, material, device, circuit, and system. This distinctive methodology is extended here by elucidating the impact on GSI of random dopant atom placement in the channel region of a MOSFET and of interconnect distributions in random logic networks in context with projected advances in device and circuit techniques.

Circuit techniques for low-power CMOS GSI

For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60/spl deg/K above room temperature.

Minimum supply voltage for bulk Si CMOS GSI

Limits on energy dissipation are investigated for bulk Si CMOS circuits at each node of the 1997 National Technology Roadmap for Semiconductors (NTRS). Physical, continuous and smooth MOSFET transregional drain current models that consider high-field effects in scaled devices, and permit trade-offs between saturation drive current and subthreshold leakage current are described and employed to model CMOS circuit performance and power dissipation at low voltages. The transregional models are used in conjunction with physical threshold voltage roll-off models and stochastic interconnect distributions, at performances, chip sizes and transistor counts forecast by the 1997 NTRS, to project optimal supply and threshold voltages, minimizing total energy dissipated by CMOS logic circuits. Techniques exploiting datapath parallelism to further reduce-supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling.

Hybrid optical-electronic logic gates in complementary metal-oxide semiconductor very-large-scale integration

Photodiodes are integrated into complementary metal-oxide semiconductor very-large-scale integration logic circuits to provide a hybrid interface between parallel-optical and electronic computing formats. This permits direct parallel transfer from an optical processor or storage element to a standard electronic system. The optical input beams may be viewed as control signals or as logical inputs that increase the system complexity and permit direct interaction of the electronic logic circuits with the optical beam states. Applications of the approach include hybrid optical-electronic logic gates, optical control of electronic data paths, and optically reconfigured very-large-scale integration circuits.

Short-channel modeling of bulk accumulation MOSFETs

Physically based short-channel effect (SCE) models are derived for bulk accumulation MOSFETs. Using the proposed models, threshold voltage rolloff, subthreshold swing, and subthreshold current can be accurately calculated; this enables physical insights into device scaling behavior, and prediction of scaling limits. The models enable optimization of accumulation MOSFETs, resulting in small SCE, and low process sensitivity. The models are equally applicable to inversion MOSFETs, and allow easy comparison between accumulation and inversion MOSFETs. Novel application areas of accumulation MOSFETs are identified where they perform better than inversion MOSFETs (better on-current and lower SCE for a given off-current). With mid-band metal gate, accumulation MOSFETs perform better than inversion MOSFETs in ultra low power applications. For poly gate CMOS, accumulation MOSFETs perform better than inversion MOSFETs in low standby power applications.

Low-power circuit advantages of the scaled accumulation FET

The trend toward higher clock frequencies has resulted in FETs being compared for their performance at the highest frequencies. Traditionally, the buried channel(BC) FET is considered to have more short channel effects than the normal surface channel inversion(SCI) FET and thus the BC FET is used only when absolutely needed. The same, more severe short channel effects behavior has been assumed for moderate to high-V/sub T/ FETs, which find use in ultra low-power applications. However, a careful investigation both at the transistor and circuit level, reveals that the BC FET is better than the SCI FET for moderate speed, ultra low-power applications.

CMOS system-on-a-chip voltage scaling beyond 50nm

The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected local and global clock rates for high performance processors. Physical short-channel MOSFET models that consider high-field effects, threshold voltage roll-off and reverse subthreshold swing roll-off are employed in tandem with stochastic interconnect distributions to calculate optimal supply voltage, threshold voltage and gate sizes that minimize total CMOS power dissipation by exploiting trade-offs between saturation drive current and subthreshold leakage current and between device size and wiring capacitance. CMOS power dissipation at its lower limit, increases exponentially with clock frequency imposing limits on performance set by heat removal. Heat removal constraints at high local clock rates, limiting the average wire length and device size within a local zone of synchrony, or macrocell, in a short-wire cellular array architecture are used to project the maximum macrocell size and count for generations beyond 100nm.

A tick based methodology for rapid predictive circuit modeling

The trend toward device miniaturization makes it necessary to scan a wide range of supply and threshold voltages and different types of FETs, so that optimal performance is obtained. Such a scan is best done by physically based models, so that predictive circuit modeling can be done to project and optimize circuit performance well into the next decade. Circuit simulators like HSPICE cannot be used for predictive modeling and thus a methodology is needed to use existing FET physical models to predict circuit performance. Such a methodology is proposed in this paper and verified against HSPICE. The proposed method works for a wide range of supply voltages, for a variety of FETs and avoids any numerical integration.

Threshold voltage roll-off model for low power bulk accumulation MOSFETs

A closed-form analytical threshold voltage roll-off model (/spl Delta/V/sub T/) for bulk accumulation MOSFETs, namely, buried channel accumulation (BCA) and surface channel accumulation (SCA), has been derived. Results show that scaling of BCA/SCA devices to the L=0.1 /spl mu/m range while maintaining performance is feasible for devices with very shallow tubs and source/drain junctions. It is also observed that for such devices, the SGA /spl Delta/V/sub T/ can be substantially smaller than the conventional surface channel inversion MOSFET /spl Delta/V/sub T/.