M. Burbidge

Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops

Charge Pump Phase locked loops are used in a variety of applications, including on chip clock synthesis, symbol timing recovery for serial data streams, and generation of frequency agile high frequency carrier signals. In many applications PLLs are embedded into larger digital systems, in consequence, analogue test access is often limited. Test motivation is thus towards methods that can either aid digital only test of the PLL, or alternatively facilitate complete self testing of the PLL. One useful characterisation technique used by PLL designers is that of closed loop phase transfer function measurement. This test allows, an estimation of the PLLs natural frequency, damping, and 3 dB bandwidth to be made from the magnitude and phase response plots. These parameters relate directly to the time domain response of the PLL and will indicate errors in the PLL circuitry. This paper provides suggestions towards test methods that use a novel maximum frequency detection technique to aid automatic measurement of the closed loop phase transfer function. In addition, techniques presented have potential for full BIST applications.

Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's

Due to a number of desirable operational and design characteristics, CP-PLLs (Charge Pump Phase locked loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and Radio frequency synthesis applications. This paper describes a simple, digital only, minimally invasive and fully automated test approach for high performance CP-PLLs that can be used to provide more information about the CP-PLL function beyond that obtained through the commonly used FLT (Frequency Lock Test). The test strategy described here allows the estimation of forward path (FP) gain and relative leakage in the forward path loop components. Applications of the test are focussed towards digital only testing of fully embedded CP-PLLs, however further test modifications could yield marked test time improvements for embedded and board level CP-PLLs incorporating multiple CP currents and or multiple loop filter (LF) configurations.

Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods

Charge-Pump Phase-locked loops are currently used in a variety of SoC signal generation applications. They ultimately determine performance of other SoC blocks, such as ADC’s, DAC’s, RF and synchronisation functions. In many situations, only simple frequency lock tests are carried out on the CP-PLL portion of a circuit, with other complex direct jitter tests being carried out indirectly at a higher system level. Although these higher level system tests must generally be carried out at some point they can be time consuming. In addition, if the PLL is designed and operating correctly the PLL system will generally have far better performance than the system it is driving. This paper investigates typical jitter output responses of CP-PLLs when subjected to selected forward path leakage faults. The evaluation platform consists of a macro level mixed signal based PLL-Model. Degradation of the PLL output is evaluated from the phase noise spectrum, jitter spectrum and sideband spur degradation. Further evaluations and analysis are supplied relating block level effects to jitter and phase noise. Investigations are made as to the efficacy of detection of these errors with simple measurement techniques. The crux of the work is thus initially to develop techniques to aid evaluation of the likely jitter performance of a CP-PLL system without resorting to direct measurement techniques.

Phase locked system design and measurement tutorial consisting of physical hardware and co-simulation environment

Phase locked loop based feedback techniques are used in a variety of system level timing, control and communication applications. Re-configurable hardware and associated simulation models have been developed with an emphasis towards teaching the fundamentals of phase locked loop systems. The material is hardware focussed and reinforces control system theory, characterisation, design, and modelling. The simulation part of the material can be used in an Internet based teaching environment.

Investigation into the Use of Hybrid Solutions for ΣΔ A/D Converter Testing

AbstractΣΔ ADCs are now extensively used in electronic system applications requiring high resolution analogue to digital interfaces. Many of these applications require low cost solutions that imply the need for efficient production test strategies for verifying performance specifications. Industrial state-of-the-art is based on DSP testing to extract dynamic performance such as THD and SNR from an FFT on a sampled bit-stream from the decimator output. This method is computationally expensive and as resolution increases, the total number of samples required also increases thus pushing total test time beyond acceptable limits. This paper proposes an alternative hybrid solution based on an initial low-cost wafer level screening test followed by a DSP based technique on marginal devices based on alternative DSP transforms. The screening test is applied to the high-frequency bit-stream output of the ΣΔ modulator and has potential for on-chip implementation. Relatively simple algorithms and cross-correlation techniques are used that can associate specific changes in the bit-stream pattern to key failure modes affecting dynamic performance parameters. A simplified supplementary DSP test for marginal devices is proposed that is less computationally intensive than FFT analysis.

Phase Locked Loop Test Methodologies

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing.