A. M. Majid

A development platform and electronic modules for automated test up to 20 Gbps

An adaptable platform for the development of customized ATE and test-support modules is described. The purpose of the platform is to provide a hardware framework for assembling combinations of specialized test modules for applications that are not well addressed by conventional general-purpose ATE alone. The platform can also be used to test, characterize, and calibrate individual modules prior to use within either a platform-based application or within a traditional ATE environment. The paper describes some of the salient features of the platform and one completed example for an all-optical packet-switching network called “Data Vortex” operating at 2.5Gbps on each of 18 channels (≫40Gbps aggregate burst data rate). Two other example modules demonstrate even higher data rates. One is a dual-channel, bidirectional 5Gbps FPGA-based module with loopback, jitter-injection, and 2:1 XOR multiplexing (up to 10Gbps). This module exploits recent advances in FPGA technology that enable very high data rates at relatively low cost. Another example module synthesizes two 10Gbps data streams using 16:1 SiGe serializers; and then combines these using an InP XOR gate to form a 20Gbps test stimulus channel. While the platform and modules have interesting characteristics, individually they do not form a complete solution. However the various possible combinations, together with special-purpose modules, may help solve some of the most difficult test applications in the near future. Therefore, this paper tries to present the key features in a way that the reader may extrapolate to future test challenges.

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

The paper describes two projects researching the development of new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about /spl plusmn/25 ps timing accuracy.

An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test

A 2-channel module for testing serial and parallel signals up to 12.8 Gbps is described. It is intended to extend the capabilities of an existing 6.4 Gbps ATE, serving as a plug-in module in an active device interface board (DIB). This prototype circuit provides (1) direct connections to ATE channels for DC parametrics and low-speed functional testing, (2) 2:1 multiplexing of 6.4 Gbps to produce 12.8 Gbps stimuli with picosecond deskew, jitter-injection, and amplitude adjustment, (3) 1:2 fanout of 12.8 Gbps DUT response signals to allow testing by two 6.4 Gbps ATE channels, (4) full-rate low-jitter active loopback path with amplitude adjustment, and (5) auxiliary outputs for parallel monitoring of both transmitted and received signals. The basic logical structure is presented, and features of the module construction are described. A novel high-bandwidth adjustable delay circuit is described, that is used for deskew and XOR-based multiplexing. The performance of the module is demonstrated between 5.0 Gbps and 12.8 Gbps.

Stretching the limits of FPGA SerDes for enhanced ATE performance

This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). The core logic block controls the test modules functionality, thereby allowing it to operate independently of the ATE. Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost. In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT. The test module can generate 10Gbps signals with ∼32ps (p-p) jitter, while the loopback path adds ∼20ps (p-p) jitter to the input signal.

Multi-function multi-GHz ATE extension using state-of-the-art FPGAs

This paper presents a multi-function multi-GHz test module designed to enhance the performance capabilities of automatic test equipment (ATE). The test module is designed with a core logic block consisting of a high-performance FPGA. It also contains an application specific logic block that is designed to perform multiple functions not possible with the FPGA alone. We demonstrate five applications: high-speed signal multiplexing up to 16Gbps, loopback testing, jitter injection, amplitude adjustment, and timing adjustment. The loopback path allows testing up to 9.28Gbps. Digital timing adjustment up to 10ns in 10ps increments, and fine adjustment up to 61ps is shown. Jitter injection up to 81ps (p-p) and amplitude adjustment over a range of 600mV are demonstrated. The core logic block itself has capabilities to generate 10Gbps output signals with 38ps (p-p, BER = 2×10−5) jitter. The test module is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). A bypass option allows signals from the ATE to pass through to the DUT, permitting use of traditional ATE functions.

Multi-Gigahertz Testing of Wafer-Level Packaged Devices

The authors are developing alternative approaches for wafer-level packaging (WLP) of high-performance, high I/O-density chips. The electrical contacts are patterned onto the wafer surface using lithographic processes in order to provide high density I/Os at a very low cost per pin. In order to fully exploit these new packaging technologies, a compatible testing approach is also needed. This paper describes one of the WLP I/O structures, a new bare-die test socket, and a low-cost multi-GHz miniature tester. Our initial objective for this WLP technology is 5 Gbps; and the operation of interconnects, the bare-die test socket, and the miniature tester at this rate and slightly higher (6.4 Gbps), was demonstrated. The miniature tester alone is demonstrated up to 8 Gbps

Performance characteristics of a 5 Gbps functional test module

This paper describes a research project that develops new low-cost techniques for testing wafer-level packaged (WLP) devices using a miniature test module connected to the top of a wafer probe card with multiple high-speed (2-5 Gbps) signals. The project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about +25 ps timing accuracy. Multi-gigahertz signals are generated with a rise time in the order of 150 ps and exhibit low jitter /spl sim/50 ps. Several programmable delay chips are used to obtain 10ns range and 10 ps resolution for adjusting critical timing signals. However, programming of these delay chips is complicated by inherent non-linearities. Currently research is under progress to calibrate these timing errors.

Practical methods for extending ATE to 40 and 50Gbps

Practical techniques for generating test signals between 10Gbps and 50Gbps are described. An historical review shows that the problem of extending ATE to higher rates has been around for several decades, with ever-increasing speed requirements. We demonstrate, in this paper that multiplexing techniques that permitted 40-50 Mbps testing in the 1980s (then using 10-20MHz ATE) can be applied to the present problem of achieved 1000x faster rates today (40-50Gbps). Some intervening steps are shown that achieved 5-10Gbps, and recently 12-24Gbps. These are extended to demonstrate synthesis of signals between 40 and 50Gbps. The paper is intended to aid others who might face similar challenges in testing high-end products prior to the day when 50Gbps ATE becomes common-place.

A 5-Gbps Test System for Wafer-Level Packaged Devices

This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a plusmn 18-ps timing accuracy. The generated signals exhibit low jitter ( ~ 35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.

Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components

Two research projects are described that develop low-cost techniques for testing multi-gigahertz devices. Each project uses commercially available components to keep costs low, and achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. An FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized emitter-coupled logic achieves multi-gigahertz data rates with about /spl plusmn/25ps timing accuracy. This paper has been adapted from (Keezer, 2005).